Simplify ARM callee-saved register handling by removing the distinction

between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 66 insertions, 175 deletions

diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 86f2b65d66..d691b2c8c1 100644
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -77,8 +77,8 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   static const unsigned DarwinCalleeSavedRegs[] = {
     // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
     // register.
-    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
-    ARM::R11, ARM::R10, ARM::R8,
+    ARM::LR, ARM::R11, ARM::R10, ARM::R8,
+    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
 
     ARM::D15, ARM::D14, ARM::D13, ARM::D12,
     ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
@@ -701,7 +701,6 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
   bool LRSpilled = false;
   unsigned NumGPRSpills = 0;
   SmallVector<unsigned, 4> UnspilledCS1GPRs;
-  SmallVector<unsigned, 4> UnspilledCS2GPRs;
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   MachineFrameInfo *MFI = MF.getFrameInfo();
 
@@ -768,23 +767,7 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
         break;
       }
     } else {
-      if (!STI.isTargetDarwin()) {
-        UnspilledCS1GPRs.push_back(Reg);
-        continue;
-      }
-
-      switch (Reg) {
-      case ARM::R4:
-      case ARM::R5:
-      case ARM::R6:
-      case ARM::R7:
-      case ARM::LR:
-        UnspilledCS1GPRs.push_back(Reg);
-        break;
-      default:
-        UnspilledCS2GPRs.push_back(Reg);
-        break;
-      }
+      UnspilledCS1GPRs.push_back(Reg);
     }
   }
 
@@ -860,13 +843,6 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
             break;
           }
         }
-      } else if (!UnspilledCS2GPRs.empty() &&
-                 !AFI->isThumb1OnlyFunction()) {
-        unsigned Reg = UnspilledCS2GPRs.front();
-        MF.getRegInfo().setPhysRegUsed(Reg);
-        AFI->setCSRegisterIsSpilled(Reg);
-        if (!isReservedReg(MF, Reg))
-          ExtraCSSpill = true;
       }
     }
 
@@ -890,17 +866,6 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
           NumExtras--;
         }
       }
-      // For non-Thumb1 functions, also check for hi-reg CS registers
-      if (!AFI->isThumb1OnlyFunction()) {
-        while (NumExtras && !UnspilledCS2GPRs.empty()) {
-          unsigned Reg = UnspilledCS2GPRs.back();
-          UnspilledCS2GPRs.pop_back();
-          if (!isReservedReg(MF, Reg)) {
-            Extras.push_back(Reg);
-            NumExtras--;
-          }
-        }
-      }
       if (Extras.size() && NumExtras == 0) {
         for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
           MF.getRegInfo().setPhysRegUsed(Extras[i]);
@@ -958,10 +923,8 @@ ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
 
   FrameReg = ARM::SP;
   Offset += SPAdj;
-  if (AFI->isGPRCalleeSavedArea1Frame(FI))
-    return Offset - AFI->getGPRCalleeSavedArea1Offset();
-  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
-    return Offset - AFI->getGPRCalleeSavedArea2Offset();
+  if (AFI->isGPRCalleeSavedAreaFrame(FI))
+    return Offset - AFI->getGPRCalleeSavedAreaOffset();
   else if (AFI->isDPRCalleeSavedAreaFrame(FI))
     return Offset - AFI->getDPRCalleeSavedAreaOffset();
 
@@ -1651,8 +1614,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 }
 
 /// Move iterator past the next bunch of callee save load / store ops for
-/// the particular spill area (1: integer area 1, 2: integer area 2,
-/// 3: fp area, 0: don't care).
+/// the particular spill area (1: integer area 1, 2: fp area, 0: don't care).
 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator &MBBI,
                                    int Opc1, int Opc2, unsigned Area,
@@ -1665,15 +1627,13 @@ static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
       unsigned Category = 0;
       switch (MBBI->getOperand(0).getReg()) {
       case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
+      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
       case ARM::LR:
         Category = 1;
         break;
-      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
-        Category = STI.isTargetDarwin() ? 2 : 1;
-        break;
       case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
       case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
-        Category = 3;
+        Category = 2;
         break;
       default:
         Done = true;
@@ -1703,7 +1663,7 @@ emitPrologue(MachineFunction &MF) const {
 
   // Determine the sizes of each callee-save spill areas and record which frame
   // belongs to which callee-save spill areas.
-  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
+  unsigned GPRCSSize = 0/*, GPRCS2Size = 0*/, DPRCSSize = 0;
   int FramePtrSpillFI = 0;
 
   // Allocate the vararg register save area. This is not counted in NumBytes.
@@ -1724,25 +1684,15 @@ emitPrologue(MachineFunction &MF) const {
     case ARM::R5:
     case ARM::R6:
     case ARM::R7:
-    case ARM::LR:
-      if (Reg == FramePtr)
-        FramePtrSpillFI = FI;
-      AFI->addGPRCalleeSavedArea1Frame(FI);
-      GPRCS1Size += 4;
-      break;
     case ARM::R8:
     case ARM::R9:
     case ARM::R10:
     case ARM::R11:
+    case ARM::LR:
       if (Reg == FramePtr)
         FramePtrSpillFI = FI;
-      if (STI.isTargetDarwin()) {
-        AFI->addGPRCalleeSavedArea2Frame(FI);
-        GPRCS2Size += 4;
-      } else {
-        AFI->addGPRCalleeSavedArea1Frame(FI);
-        GPRCS1Size += 4;
-      }
+      AFI->addGPRCalleeSavedAreaFrame(FI);
+      GPRCSSize += 4;
       break;
     default:
       AFI->addDPRCalleeSavedAreaFrame(FI);
@@ -1750,15 +1700,11 @@ emitPrologue(MachineFunction &MF) const {
     }
   }
 
-  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
-  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
+  // Build the new SUBri to adjust SP for integer callee-save spill area.
+  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCSSize);
   movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
 
   // Set FP to point to the stack slot that contains the previous FP.
-  // For Darwin, FP is R7, which has now been stored in spill area 1.
-  // Otherwise, if this is not Darwin, all the callee-saved registers go
-  // into spill area 1, including the FP in R11.  In either case, it is
-  // now safe to emit this assignment.
   bool HasFP = hasFP(MF);
   if (HasFP) {
     unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
@@ -1768,25 +1714,19 @@ emitPrologue(MachineFunction &MF) const {
     AddDefaultCC(AddDefaultPred(MIB));
   }
 
-  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
-  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
-
   // Build the new SUBri to adjust SP for FP callee-save spill area.
-  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
   emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
 
   // Determine starting offsets of spill areas.
-  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
-  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
-  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
+  unsigned DPRCSOffset  = NumBytes - (GPRCSSize + DPRCSSize);
+  unsigned GPRCSOffset = DPRCSOffset + DPRCSSize;
   if (HasFP)
     AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
                                 NumBytes);
-  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
-  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
+  AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset);
   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
 
-  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
+  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 2, STI);
   NumBytes = DPRCSOffset;
   if (NumBytes) {
     // Adjust SP after all the callee-save spills.
@@ -1801,8 +1741,7 @@ emitPrologue(MachineFunction &MF) const {
     AFI->setShouldRestoreSPFromFP(true);
   }
 
-  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
-  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
+  AFI->setGPRCalleeSavedAreaSize(GPRCSSize);
   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
 
   // If we need dynamic stack realignment, do it here. Be paranoid and make
@@ -1904,8 +1843,7 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
     }
 
     // Move SP to start of FP callee save spill area.
-    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
-                 AFI->getGPRCalleeSavedArea2Size() +
+    NumBytes -= (AFI->getGPRCalleeSavedAreaSize() +
                  AFI->getDPRCalleeSavedAreaSize());
 
     // Reset SP based on frame pointer only if the stack frame extends beyond
@@ -1931,17 +1869,13 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
     } else if (NumBytes)
       emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
 
-    // Move SP to start of integer callee save spill area 2.
-    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
+    // Move SP to start of integer callee save spill area.
+    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 2, STI);
     emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
 
-    // Move SP to start of integer callee save spill area 1.
-    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
-    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
-
     // Move SP to SP upon entry to the function.
     movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
-    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
+    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedAreaSize());
   }
 
   if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
diff --git a/lib/Target/ARM/ARMMachineFunctionInfo.h b/lib/Target/ARM/ARMMachineFunctionInfo.h
index 514c26b4da..22f3750a42 100644
--- a/lib/Target/ARM/ARMMachineFunctionInfo.h
+++ b/lib/Target/ARM/ARMMachineFunctionInfo.h
@@ -55,28 +55,23 @@ class ARMFunctionInfo : public MachineFunctionInfo {
   /// spill stack offset.
   unsigned FramePtrSpillOffset;
 
-  /// GPRCS1Offset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved
-  /// register spills areas. For Mac OS X:
+  /// GPRCSOffset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved
+  /// register spills areas (excluding R9 for Mac OS X):
   ///
-  /// GPR callee-saved (1) : r4, r5, r6, r7, lr
-  /// --------------------------------------------
-  /// GPR callee-saved (2) : r8, r10, r11
+  /// GPR callee-saved (1) : r4, r5, r6, r7, r8, r9, r10, r11, lr
   /// --------------------------------------------
   /// DPR callee-saved : d8 - d15
-  unsigned GPRCS1Offset;
-  unsigned GPRCS2Offset;
+  unsigned GPRCSOffset;
   unsigned DPRCSOffset;
 
-  /// GPRCS1Size, GPRCS2Size, DPRCSSize - Sizes of callee saved register spills
+  /// GPRCSSize, GPRCS2Size, DPRCSSize - Sizes of callee saved register spills
   /// areas.
-  unsigned GPRCS1Size;
-  unsigned GPRCS2Size;
+  unsigned GPRCSSize;
   unsigned DPRCSSize;
 
-  /// GPRCS1Frames, GPRCS2Frames, DPRCSFrames - Keeps track of frame indices
+  /// GPRCSFrames, GPRCS2Frames, DPRCSFrames - Keeps track of frame indices
   /// which belong to these spill areas.
-  BitVector GPRCS1Frames;
-  BitVector GPRCS2Frames;
+  BitVector GPRCSFrames;
   BitVector DPRCSFrames;
 
   /// SpilledCSRegs - A BitVector mask of all spilled callee-saved registers.
@@ -101,9 +96,9 @@ public:
     hasThumb2(false),
     VarArgsRegSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false),
     LRSpilledForFarJump(false),
-    FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
-    GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
-    GPRCS1Frames(0), GPRCS2Frames(0), DPRCSFrames(0),
+    FramePtrSpillOffset(0), GPRCSOffset(0), DPRCSOffset(0),
+    GPRCSSize(0), DPRCSSize(0),
+    GPRCSFrames(0), DPRCSFrames(0),
     JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0),
     HasITBlocks(false) {}
 
@@ -112,9 +107,9 @@ public:
     hasThumb2(MF.getTarget().getSubtarget<ARMSubtarget>().hasThumb2()),
     VarArgsRegSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false),
     LRSpilledForFarJump(false),
-    FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
-    GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
-    GPRCS1Frames(32), GPRCS2Frames(32), DPRCSFrames(32),
+    FramePtrSpillOffset(0), GPRCSOffset(0), DPRCSOffset(0),
+    GPRCSSize(0), DPRCSSize(0),
+    GPRCSFrames(32), DPRCSFrames(32),
     SpilledCSRegs(MF.getTarget().getRegisterInfo()->getNumRegs()),
     JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0),
     HasITBlocks(false) {}
@@ -138,31 +133,22 @@ public:
   unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; }
   void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; }
 
-  unsigned getGPRCalleeSavedArea1Offset() const { return GPRCS1Offset; }
-  unsigned getGPRCalleeSavedArea2Offset() const { return GPRCS2Offset; }
+  unsigned getGPRCalleeSavedAreaOffset() const { return GPRCSOffset; }
   unsigned getDPRCalleeSavedAreaOffset()  const { return DPRCSOffset; }
 
-  void setGPRCalleeSavedArea1Offset(unsigned o) { GPRCS1Offset = o; }
-  void setGPRCalleeSavedArea2Offset(unsigned o) { GPRCS2Offset = o; }
+  void setGPRCalleeSavedAreaOffset(unsigned o) { GPRCSOffset = o; }
   void setDPRCalleeSavedAreaOffset(unsigned o)  { DPRCSOffset = o; }
 
-  unsigned getGPRCalleeSavedArea1Size() const { return GPRCS1Size; }
-  unsigned getGPRCalleeSavedArea2Size() const { return GPRCS2Size; }
+  unsigned getGPRCalleeSavedAreaSize() const { return GPRCSSize; }
   unsigned getDPRCalleeSavedAreaSize()  const { return DPRCSSize; }
 
-  void setGPRCalleeSavedArea1Size(unsigned s) { GPRCS1Size = s; }
-  void setGPRCalleeSavedArea2Size(unsigned s) { GPRCS2Size = s; }
+  void setGPRCalleeSavedAreaSize(unsigned s) { GPRCSSize = s; }
   void setDPRCalleeSavedAreaSize(unsigned s)  { DPRCSSize = s; }
 
-  bool isGPRCalleeSavedArea1Frame(int fi) const {
-    if (fi < 0 || fi >= (int)GPRCS1Frames.size())
-      return false;
-    return GPRCS1Frames[fi];
-  }
-  bool isGPRCalleeSavedArea2Frame(int fi) const {
-    if (fi < 0 || fi >= (int)GPRCS2Frames.size())
+  bool isGPRCalleeSavedAreaFrame(int fi) const {
+    if (fi < 0 || fi >= (int)GPRCSFrames.size())
       return false;
-    return GPRCS2Frames[fi];
+    return GPRCSFrames[fi];
   }
   bool isDPRCalleeSavedAreaFrame(int fi) const {
     if (fi < 0 || fi >= (int)DPRCSFrames.size())
@@ -170,28 +156,16 @@ public:
     return DPRCSFrames[fi];
   }
 
-  void addGPRCalleeSavedArea1Frame(int fi) {
-    if (fi >= 0) {
-      int Size = GPRCS1Frames.size();
-      if (fi >= Size) {
-        Size *= 2;
-        if (fi >= Size)
-          Size = fi+1;
-        GPRCS1Frames.resize(Size);
-      }
-      GPRCS1Frames[fi] = true;
-    }
-  }
-  void addGPRCalleeSavedArea2Frame(int fi) {
+  void addGPRCalleeSavedAreaFrame(int fi) {
     if (fi >= 0) {
-      int Size = GPRCS2Frames.size();
+      int Size = GPRCSFrames.size();
       if (fi >= Size) {
         Size *= 2;
         if (fi >= Size)
           Size = fi+1;
-        GPRCS2Frames.resize(Size);
+        GPRCSFrames.resize(Size);
       }
-      GPRCS2Frames[fi] = true;
+      GPRCSFrames[fi] = true;
     }
   }
   void addDPRCalleeSavedAreaFrame(int fi) {
diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp
index a21a3da10b..44eafcb3f6 100644
--- a/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -597,10 +597,8 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
                MF.getFrameInfo()->getStackSize() + SPAdj;
 
-  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
-    Offset -= AFI->getGPRCalleeSavedArea1Offset();
-  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
-    Offset -= AFI->getGPRCalleeSavedArea2Offset();
+  if (AFI->isGPRCalleeSavedAreaFrame(FrameIndex))
+    Offset -= AFI->getGPRCalleeSavedAreaOffset();
   else if (MF.getFrameInfo()->hasVarSizedObjects()) {
     assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
     // There are alloca()'s in this function, must reference off the frame
@@ -709,7 +707,7 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   // Determine the sizes of each callee-save spill areas and record which frame
   // belongs to which callee-save spill areas.
-  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
+  unsigned GPRCSSize = 0, DPRCSSize = 0;
   int FramePtrSpillFI = 0;
 
   if (VARegSaveSize)
@@ -729,25 +727,15 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
     case ARM::R5:
     case ARM::R6:
     case ARM::R7:
-    case ARM::LR:
-      if (Reg == FramePtr)
-        FramePtrSpillFI = FI;
-      AFI->addGPRCalleeSavedArea1Frame(FI);
-      GPRCS1Size += 4;
-      break;
     case ARM::R8:
     case ARM::R9:
     case ARM::R10:
     case ARM::R11:
+    case ARM::LR:
       if (Reg == FramePtr)
         FramePtrSpillFI = FI;
-      if (STI.isTargetDarwin()) {
-        AFI->addGPRCalleeSavedArea2Frame(FI);
-        GPRCS2Size += 4;
-      } else {
-        AFI->addGPRCalleeSavedArea1Frame(FI);
-        GPRCS1Size += 4;
-      }
+      AFI->addGPRCalleeSavedAreaFrame(FI);
+      GPRCSSize += 4;
       break;
     default:
       AFI->addDPRCalleeSavedAreaFrame(FI);
@@ -769,12 +757,10 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
   }
 
   // Determine starting offsets of spill areas.
-  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
-  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
-  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
+  unsigned DPRCSOffset  = NumBytes - (GPRCSSize + DPRCSSize);
+  unsigned GPRCSOffset = DPRCSOffset + DPRCSSize;
   AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
-  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
-  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
+  AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset);
   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
 
   NumBytes = DPRCSOffset;
@@ -787,8 +773,7 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
     MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
                              AFI->getFramePtrSpillOffset());
 
-  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
-  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
+  AFI->setGPRCalleeSavedAreaSize(GPRCSSize);
   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
 
   // If we need a base pointer, set it up here. It's whatever the value
@@ -849,8 +834,7 @@ void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
     }
 
     // Move SP to start of FP callee save spill area.
-    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
-                 AFI->getGPRCalleeSavedArea2Size() +
+    NumBytes -= (AFI->getGPRCalleeSavedAreaSize() +
                  AFI->getDPRCalleeSavedAreaSize());
 
     if (AFI->shouldRestoreSPFromFP()) {
diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll
index b8c543b1bd..9f1a44a5fe 100644
--- a/test/CodeGen/ARM/lsr-code-insertion.ll
+++ b/test/CodeGen/ARM/lsr-code-insertion.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -stats |& grep {38.*Number of machine instrs printed}
+; RUN: llc < %s -stats |& grep {36.*Number of machine instrs printed}
 ; RUN: llc < %s -stats |& not grep {.*Number of re-materialization}
 ; This test really wants to check that the resultant "cond_true" block only 
 ; has a single store in it, and that cond_true55 only has code to materialize 
diff --git a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
index f91e1c9feb..a0caf3b76a 100644
--- a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
+++ b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
@@ -32,15 +32,14 @@
 
 define fastcc i32 @parse_percent_token() nounwind {
 entry:
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
+; CHECK: itt eq
+; CHECK: itt eq
+; CHECK: itt eq
+; CHECK: itt eq
+; CHECK: itt eq
 ; CHECK: moveq r0
 ; CHECK-NOT: LBB0_
-; CHECK: ldreq
-; CHECK: popeq
+; CHECK: ldmiaeq
   switch i32 undef, label %bb7 [
     i32 37, label %bb43
     i32 48, label %bb5