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| author | Hal Finkel <hfinkel@anl.gov> | 2014-03-27 21:26:33 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-27 21:26:33 +0000 |
| commit | 276d854549f851c7d09c2e6a61bc2ca4e6973f6b (patch) | |
| tree | aa9b9f90ae7738fdb58c48eea312554e5bc4bfd8 | |
| parent | b5e6ddca565a437dcc25b28c756cde00b6901054 (diff) | |
| download | llvm-276d854549f851c7d09c2e6a61bc2ca4e6973f6b.tar.gz llvm-276d854549f851c7d09c2e6a61bc2ca4e6973f6b.tar.bz2 llvm-276d854549f851c7d09c2e6a61bc2ca4e6973f6b.tar.xz | |
[PowerPC] Expand v2i64 shifts
These operations need to be expanded during legalization so that isel does not
crash. In theory, we might be able to custom lower some of these. That,
however, would need to be follow-up work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204963 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/vsx.ll | 42 |
2 files changed, 46 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 6f640183f9..16ff0eb7d7 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -581,6 +581,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::ADD, MVT::v2i64, Expand); setOperationAction(ISD::SUB, MVT::v2i64, Expand); + setOperationAction(ISD::SHL, MVT::v2i64, Expand); + setOperationAction(ISD::SRA, MVT::v2i64, Expand); + setOperationAction(ISD::SRL, MVT::v2i64, Expand); + setOperationAction(ISD::LOAD, MVT::v2i64, Promote); AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); setOperationAction(ISD::STORE, MVT::v2i64, Promote); diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index 2524251a20..89499560b3 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -487,3 +487,45 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) { ; CHECK: blr } +define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) { + %v = shl <2 x i64> %a, %b + ret <2 x i64> %v + +; CHECK-LABEL: @test60 +; This should scalarize, and the current code quality is not good. +; CHECK: stxvd2x +; CHECK: stxvd2x +; CHECK: sld +; CHECK: sld +; CHECK: lxvd2x +; CHECK: blr +} + +define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) { + %v = lshr <2 x i64> %a, %b + ret <2 x i64> %v + +; CHECK-LABEL: @test61 +; This should scalarize, and the current code quality is not good. +; CHECK: stxvd2x +; CHECK: stxvd2x +; CHECK: srd +; CHECK: srd +; CHECK: lxvd2x +; CHECK: blr +} + +define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) { + %v = ashr <2 x i64> %a, %b + ret <2 x i64> %v + +; CHECK-LABEL: @test62 +; This should scalarize, and the current code quality is not good. +; CHECK: stxvd2x +; CHECK: stxvd2x +; CHECK: srad +; CHECK: srad +; CHECK: lxvd2x +; CHECK: blr +} + |