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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-02-28 18:22:56 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-02-28 18:22:56 +0000 |
| commit | 2a80d7db79f9ed8744101eb8a47a86aa482f7c52 (patch) | |
| tree | d7567234b043a027fce4c5e81f5d6baf399d3a3c | |
| parent | 0164f27742eee258409466b1a3a63bec222e84d2 (diff) | |
| download | llvm-2a80d7db79f9ed8744101eb8a47a86aa482f7c52.tar.gz llvm-2a80d7db79f9ed8744101eb8a47a86aa482f7c52.tar.bz2 llvm-2a80d7db79f9ed8744101eb8a47a86aa482f7c52.tar.xz | |
Fixed operand of SC microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202526 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/Mips/MicroMipsInstrInfo.td | 3 | ||||
| -rw-r--r-- | test/CodeGen/Mips/micromips-atomic.ll | 18 |
3 files changed, 23 insertions, 1 deletions
diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index c574f549a1..a543840132 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -611,6 +611,9 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst, Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + if (Inst.getOpcode() == Mips::SC_MM) + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Reg)); Inst.addOperand(MCOperand::CreateReg(Base)); Inst.addOperand(MCOperand::CreateImm(Offset)); diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 639e3deb75..4147405571 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -53,10 +53,11 @@ class LLBaseMM<string opstr, RegisterOperand RO> : } class SCBaseMM<string opstr, RegisterOperand RO> : - InstSE<(outs), (ins RO:$rt, mem_mm_12:$addr), + InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr), !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { let DecoderMethod = "DecodeMemMMImm12"; let mayStore = 1; + let Constraints = "$rt = $dst"; } class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, diff --git a/test/CodeGen/Mips/micromips-atomic.ll b/test/CodeGen/Mips/micromips-atomic.ll new file mode 100644 index 0000000000..a50e0b7850 --- /dev/null +++ b/test/CodeGen/Mips/micromips-atomic.ll @@ -0,0 +1,18 @@ +; RUN: llc %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -filetype=asm \ +; RUN: -relocation-model=pic -o - | FileCheck %s + +@x = common global i32 0, align 4 + +define i32 @AtomicLoadAdd32(i32 %incr) nounwind { +entry: + %0 = atomicrmw add i32* @x, i32 %incr monotonic + ret i32 %0 + +; CHECK-LABEL: AtomicLoadAdd32: +; CHECK: lw $[[R0:[0-9]+]], %got(x) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 +; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: beqz $[[R2]], $[[BB0]] +} |