ARM: Remove a (false) dependency on the memoryoperand's value as we do not use

it at the moment.
This allows to form more paired loads even when stack coloring pass destroys the
memoryoperand's value.

<rdar://problem/13978317>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184492 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 46 insertions, 3 deletions

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index c8ed5760f9..4e97ddaa2c 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1602,8 +1602,9 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
     return false;
 
   // Make sure the base address satisfies i64 ld / st alignment requirement.
+  // At the moment, we ignore the memoryoperand's value.
+  // If we want to use AliasAnalysis, we should check it accordingly.
   if (!Op0->hasOneMemOperand() ||
-      !(*Op0->memoperands_begin())->getValue() ||
       (*Op0->memoperands_begin())->isVolatile())
     return false;
 
diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
index b0644d1743..e599f43fad 100644
--- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
+++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
@@ -24,7 +24,14 @@ entry:
 }
 
 ; CHECK: main:
-; CHECK: ldm     r0, {r2, r3}
+; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
+; CHECK: movt [[BASE]], :upper16:static_val
+; ldm is not formed when the coalescer failed to coalesce everything.
+; CHECK: ldr     r2, {{\[}}[[BASE]]{{\]}}
+; CHECK: ldr     [[TMP:r[0-9]+]], {{\[}}[[BASE]], #4{{\]}}
+; CHECK: movw r0, #555
+; Currently the coalescer misses this opportunity.
+; CHECK: mov r3, [[TMP]]
 define i32 @main() {
 entry:
   call void (i32, ...)* @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val)
@@ -47,7 +54,14 @@ entry:
 }
 
 ; CHECK: main_fixed_arg:
-; CHECK: ldm     r0, {r2, r3}
+; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
+; CHECK: movt [[BASE]], :upper16:static_val
+; ldm is not formed when the coalescer failed to coalesce everything.
+; CHECK: ldr     r2, {{\[}}[[BASE]]{{\]}}
+; CHECK: ldr     [[TMP:r[0-9]+]], {{\[}}[[BASE]], #4{{\]}}
+; CHECK: movw r0, #555
+; Currently the coalescer misses this opportunity.
+; CHECK: mov r3, [[TMP]]
 define i32 @main_fixed_arg() {
 entry:
   call void (i32, %struct_t*)* @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val)
diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll
index 73b546d021..4abf6e6528 100644
--- a/test/CodeGen/ARM/ldrd.ll
+++ b/test/CodeGen/ARM/ldrd.ll
@@ -67,3 +67,31 @@ bb:                                               ; preds = %bb, %entry
 return:                                           ; preds = %bb, %entry
   ret void
 }
+
+; rdar://13978317
+; Pair of loads not formed when lifetime markers are set.
+%struct.Test = type { i32, i32, i32 }
+
+@TestVar = external global %struct.Test
+
+define void @Func1() nounwind ssp {
+; CHECK: @Func1
+entry: 
+; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
+; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}}
+; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4]
+; A8-NEXT: add [[FIELD1]], [[FIELD2]]
+; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}}
+  %orig_blocks = alloca [256 x i16], align 2
+  %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind
+  %tmp1 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 1), align 4
+  %tmp2 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 2), align 4
+  %add = add nsw i32 %tmp2, %tmp1
+  store i32 %add, i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 0), align 4
+  call void @llvm.lifetime.end(i64 512, i8* %0) nounwind
+  ret void
+}
+
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
+declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind