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authorChris Lattner <sabre@nondot.org>2002-11-02 19:27:56 +0000
committerChris Lattner <sabre@nondot.org>2002-11-02 19:27:56 +0000
commit2df035bb3c3d4296fd1a77fb114611e6779752f0 (patch)
tree0006ee7a6a6b04b370c1c5229ee4a01eb2820f99
parent6a353ed5da89fffd5436576dc5ab6c081bf6aa97 (diff)
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Implement unconditional branching support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4498 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/InstSelectSimple.cpp9
-rw-r--r--lib/Target/X86/X86ISelSimple.cpp9
-rw-r--r--lib/Target/X86/X86InstrInfo.def3
3 files changed, 20 insertions, 1 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index 144dc228d1..253f3ddcb0 100644
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -55,6 +55,7 @@ namespace {
// fixed X86 code for each instruction.
//
void visitReturnInst(ReturnInst &RI);
+ void visitBranchInst(BranchInst &BI);
void visitAdd(BinaryOperator &B);
void visitShiftInst(ShiftInst &I);
@@ -162,6 +163,14 @@ void ISel::visitReturnInst(ReturnInst &I) {
BuildMI(BB, X86::RET, 0);
}
+void ISel::visitBranchInst(BranchInst &BI) {
+ if (BI.isConditional()) // Only handles unconditional branches so far...
+ visitInstruction(BI);
+
+ BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
+}
+
+
/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
/// for constant immediate shift values, and for constant immediate
/// shift values equal to 1. Even the general case is sort of special,
diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 144dc228d1..253f3ddcb0 100644
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -55,6 +55,7 @@ namespace {
// fixed X86 code for each instruction.
//
void visitReturnInst(ReturnInst &RI);
+ void visitBranchInst(BranchInst &BI);
void visitAdd(BinaryOperator &B);
void visitShiftInst(ShiftInst &I);
@@ -162,6 +163,14 @@ void ISel::visitReturnInst(ReturnInst &I) {
BuildMI(BB, X86::RET, 0);
}
+void ISel::visitBranchInst(BranchInst &BI) {
+ if (BI.isConditional()) // Only handles unconditional branches so far...
+ visitInstruction(BI);
+
+ BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
+}
+
+
/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
/// for constant immediate shift values, and for constant immediate
/// shift values equal to 1. Even the general case is sort of special,
diff --git a/lib/Target/X86/X86InstrInfo.def b/lib/Target/X86/X86InstrInfo.def
index 519e7680d7..327c4e64f6 100644
--- a/lib/Target/X86/X86InstrInfo.def
+++ b/lib/Target/X86/X86InstrInfo.def
@@ -33,8 +33,9 @@ I(PHI , "phi", 0, 0)
// The second instruction must always be the noop instruction: (FIXME, not yet)
I(NOOP , "nop", 0, X86II::Void) // nop 90
-// Miscellaneous instructions
+// Flow control instructions
I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB
+I(JMP , "jmp", M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w
// Move instructions
I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r