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author | Tim Northover <Tim.Northover@arm.com> | 2012-11-20 09:56:11 +0000 |
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committer | Tim Northover <Tim.Northover@arm.com> | 2012-11-20 09:56:11 +0000 |
commit | 310f248c22c5a20eaa4de1e612af3338a89144f3 (patch) | |
tree | 3e4fc3bb0a0e1b1d85dfd2d38284f0c44f494f8a | |
parent | 4fe5405bdd2c76108e2d40020374a13d243d14c2 (diff) | |
download | llvm-310f248c22c5a20eaa4de1e612af3338a89144f3.tar.gz llvm-310f248c22c5a20eaa4de1e612af3338a89144f3.tar.bz2 llvm-310f248c22c5a20eaa4de1e612af3338a89144f3.tar.xz |
Fix physical register liveness calculations:
+ Take account of clobbers
+ Give outputs priority over inputs since they happen later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168360 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/CodeGen/MachineInstrBundle.h | 5 | ||||
-rw-r--r-- | lib/CodeGen/MachineBasicBlock.cpp | 15 | ||||
-rw-r--r-- | lib/CodeGen/MachineInstrBundle.cpp | 6 | ||||
-rw-r--r-- | test/CodeGen/ARM/domain-conv-vmovs.ll | 20 |
4 files changed, 34 insertions, 12 deletions
diff --git a/include/llvm/CodeGen/MachineInstrBundle.h b/include/llvm/CodeGen/MachineInstrBundle.h index 854ba06209..3c60ad1f29 100644 --- a/include/llvm/CodeGen/MachineInstrBundle.h +++ b/include/llvm/CodeGen/MachineInstrBundle.h @@ -149,16 +149,13 @@ public: /// PhysRegInfo - Information about a physical register used by a set of /// operands. struct PhysRegInfo { - /// Clobbers - Reg or an overlapping register is defined, or a regmask + /// Clobbers - Reg or an overlapping register is defined, or a regmask /// clobbers Reg. bool Clobbers; /// Defines - Reg or a super-register is defined. bool Defines; - /// DefinesOverlap - Reg or an overlapping register is defined. - bool DefinesOverlap; - /// Reads - Read or a super-register is read. bool Reads; diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index 18d021d521..4406c89aba 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -982,7 +982,6 @@ MachineBasicBlock::LivenessQueryResult MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, MachineInstr *MI, unsigned Neighborhood) { - unsigned N = Neighborhood; MachineBasicBlock *MBB = MI->getParent(); @@ -997,14 +996,18 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, MachineOperandIteratorBase::PhysRegInfo Analysis = MIOperands(I).analyzePhysReg(Reg, TRI); - if (Analysis.Kills) + if (Analysis.Defines) + // Outputs happen after inputs so they take precedence if both are + // present. + return Analysis.DefinesDead ? LQR_Dead : LQR_Live; + + if (Analysis.Kills || Analysis.Clobbers) // Register killed, so isn't live. return LQR_Dead; - else if (Analysis.DefinesOverlap || Analysis.ReadsOverlap) + else if (Analysis.ReadsOverlap) // Defined or read without a previous kill - live. - return (Analysis.Defines || Analysis.Reads) ? - LQR_Live : LQR_OverlappingLive; + return Analysis.Reads ? LQR_Live : LQR_OverlappingLive; } while (I != MBB->begin() && --N > 0); } @@ -1036,7 +1039,7 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, return (Analysis.Reads) ? LQR_Live : LQR_OverlappingLive; - else if (Analysis.DefinesOverlap) + else if (Analysis.Clobbers || Analysis.Defines) // Defined (but not read) therefore cannot have been live. return LQR_Dead; } diff --git a/lib/CodeGen/MachineInstrBundle.cpp b/lib/CodeGen/MachineInstrBundle.cpp index 1f7fbfc719..70f97dedaa 100644 --- a/lib/CodeGen/MachineInstrBundle.cpp +++ b/lib/CodeGen/MachineInstrBundle.cpp @@ -281,7 +281,7 @@ MachineOperandIteratorBase::PhysRegInfo MachineOperandIteratorBase::analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) { bool AllDefsDead = true; - PhysRegInfo PRI = {false, false, false, false, false, false, false}; + PhysRegInfo PRI = {false, false, false, false, false, false}; assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "analyzePhysReg not given a physical register!"); @@ -305,7 +305,9 @@ MachineOperandIteratorBase::analyzePhysReg(unsigned Reg, // Reg or a super-reg is read, and perhaps killed also. PRI.Reads = true; PRI.Kills = MO.isKill(); - } if (IsRegOrOverlapping && MO.readsReg()) { + } + + if (IsRegOrOverlapping && MO.readsReg()) { PRI.ReadsOverlap = true;// Reg or an overlapping register is read. } diff --git a/test/CodeGen/ARM/domain-conv-vmovs.ll b/test/CodeGen/ARM/domain-conv-vmovs.ll index a5c4114458..0ebac94e13 100644 --- a/test/CodeGen/ARM/domain-conv-vmovs.ll +++ b/test/CodeGen/ARM/domain-conv-vmovs.ll @@ -98,3 +98,23 @@ define i32 @test_vmovs_no_sreg(i32 %in) { ret i32 %resi } + + +; The point of this test is: +; + Make sure s1 is live before the BL +; + Make sure s1 is clobbered by the BL +; + Convince LLVM to emit a VMOV to S0 +; + Convince LLVM to domain-convert this. + +; When all of those are satisfied, LLVM should *not* mark s1 as an implicit-use +; because it's dead. + +declare float @clobbers_s1(float, float) + +define <2 x float> @test_clobbers_recognised(<2 x float> %invec, float %val) { + %elt = call float @clobbers_s1(float %val, float %val) + + %vec = insertelement <2 x float> %invec, float %elt, i32 0 + %res = fadd <2 x float> %vec, %vec + ret <2 x float> %res +} |