Rewrite Dwarf number handling per review comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43918 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 206 insertions, 155 deletions

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 1432d1306d..6d17f4cd80 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -665,47 +665,100 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
 // for exception handling.
 
 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const {
-  int n = X86GenRegisterInfo::getDwarfRegNum(RegNo);
+  static const int dwarf_64bit[] = {
+  // none,   ah,   al,   ax,   bh,   bl,   bp,  bpl,   bx,   ch, 
+       -1,    0,    0,    0,    3,    3,    6,    6,    3,    2,      
+  //   cl,   cx,   dh,   di,  dil,   dl,   dx,  eax,  ebp,  ebx,
+        2,    2,    1,    5,    5,    1,    1,    0,    6,    3,
+  //  ecx,  edi,  edx,  efl,  eip,  esi,  esp,  fp0,  fp1,  fp2,
+        2,    5,    1,   -1,   16,    4,    7,   -1,   -1,   -1,
+  //  fp3,  fp4,  fp5,  fp6,   ip,  mm0,  mm1,  mm2,  mm3,  mm4,
+       -1,   -1,   -1,   -1,   16,   41,   42,   43,   44,   45,
+  //  mm5,  mm6,  mm7,  r10, r10b, r10d, r10w,  r11, r11b, r11d, 
+       46,   47,   48,   10,   10,   10,   10,   11,   11,   11,
+  // r11w,  r12, r12b, r12d, r12w,  r13, r13b, r13d, r13w,  r14,
+       11,   12,   12,   12,   12,   13,   13,   13,   13,   14,
+  // r14b, r14d, r14w,  r15, r15b, r15d, r15w,   r8,  r8b,  r8d,
+       14,   14,   14,   15,   15,   15,   15,    8,    8,    8,
+  //  r8w,   r9,  r9b,  r9d,  r9w,  rax,  rbp,  rbx,  rcx,  rdi,
+        8,    9,    9,    9,    9,    0,    6,    3,    2,    5,
+  //  rdx,  rip,  rsi,  rsp,   si,  sil,   sp,  spl,  st0,  st1,  
+        1,   16,    4,    7,    4,    4,    7,    7,   33,   34,
+  //  st2,  st3,  st4,  st5,  st6,  st7, xmm0, xmm1,xmm10,xmm11,
+       35,   36,   37,   38,   39,   40,   17,   18,   27,   28,  
+  //xmm12,xmm13,xmm14,xmm15, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, 
+       29,   30,   31,   32,   19,   20,   21,   22,   23,   24,
+  // xmm8, xmm9
+       25,   26 };
+
+  static const int dwarf_32bit_darwin[] = {
+  // none,   ah,   al,   ax,   bh,   bl,   bp,  bpl,   bx,   ch, 
+       -1,    0,    0,    0,    3,    3,    4,    4,    3,    1,      
+  //   cl,   cx,   dh,   di,  dil,   dl,   dx,  eax,  ebp,  ebx,
+        1,    1,    2,    7,    7,    2,    2,    0,    4,    3,
+  //  ecx,  edi,  edx,  efl,  eip,  esi,  esp,  fp0,  fp1,  fp2,
+        1,    7,    2,   -1,    8,    6,    5,   -1,   -1,   -1,
+  //  fp3,  fp4,  fp5,  fp6,   ip,  mm0,  mm1,  mm2,  mm3,  mm4,
+       -1,   -1,   -1,   -1,    8,   29,   30,   31,   32,   33,
+  //  mm5,  mm6,  mm7,  r10, r10b, r10d, r10w,  r11, r11b, r11d, 
+       34,   35,   36,   -1,   -1,   -1,   -1,   -1,   -1,   -1,
+  // r11w,  r12, r12b, r12d, r12w,  r13, r13b, r13d, r13w,  r14,
+       -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,
+  // r14b, r14d, r14w,  r15, r15b, r15d, r15w,   r8,  r8b,  r8d,
+       -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,
+  //  r8w,   r9,  r9b,  r9d,  r9w,  rax,  rbp,  rbx,  rcx,  rdi,
+       -1,   -1,   -1,   -1,   -1,    0,    4,    3,    1,    7,
+  //  rdx,  rip,  rsi,  rsp,   si,  sil,   sp,  spl,  st0,  st1,  
+        2,    8,    6,    5,    6,    6,    5,    5,   12,   13,
+  //  st2,  st3,  st4,  st5,  st6,  st7, xmm0, xmm1,xmm10,xmm11,
+       14,   15,   16,   17,   18,   19,   21,   22,   -1,   -1,  
+  //xmm12,xmm13,xmm14,xmm15, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, 
+       -1,   -1,   -1,   -1,   23,   24,   25,   26,   27,   28,
+  // xmm8, xmm9
+       -1,   -1 };
+
+  static const int dwarf_32bit_linux[] = {
+  // none,   ah,   al,   ax,   bh,   bl,   bp,  bpl,   bx,   ch, 
+       -1,    0,    0,    0,    3,    3,    5,    5,    3,    1,      
+  //   cl,   cx,   dh,   di,  dil,   dl,   dx,  eax,  ebp,  ebx,
+        1,    1,    2,    7,    7,    2,    2,    0,    5,    3,
+  //  ecx,  edi,  edx,  efl,  eip,  esi,  esp,  fp0,  fp1,  fp2,
+        1,    7,    2,   -1,    8,    6,    4,   -1,   -1,   -1,
+  //  fp3,  fp4,  fp5,  fp6,   ip,  mm0,  mm1,  mm2,  mm3,  mm4,
+       -1,   -1,   -1,   -1,    8,   29,   30,   31,   32,   33,
+  //  mm5,  mm6,  mm7,  r10, r10b, r10d, r10w,  r11, r11b, r11d, 
+       34,   35,   36,   -1,   -1,   -1,   -1,   -1,   -1,   -1,
+  // r11w,  r12, r12b, r12d, r12w,  r13, r13b, r13d, r13w,  r14,
+       -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,
+  // r14b, r14d, r14w,  r15, r15b, r15d, r15w,   r8,  r8b,  r8d,
+       -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1,
+  //  r8w,   r9,  r9b,  r9d,  r9w,  rax,  rbp,  rbx,  rcx,  rdi,
+       -1,   -1,   -1,   -1,   -1,    0,    5,    3,    1,    7,
+  //  rdx,  rip,  rsi,  rsp,   si,  sil,   sp,  spl,  st0,  st1,  
+        2,    8,    6,    4,    6,    6,    4,    4,   11,   12,
+  //  st2,  st3,  st4,  st5,  st6,  st7, xmm0, xmm1,xmm10,xmm11,
+       13,   14,   15,   16,   17,   18,   21,   22,   -1,   -1,  
+  //xmm12,xmm13,xmm14,xmm15, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, 
+       -1,   -1,   -1,   -1,   23,   24,   25,   26,   27,   28,
+  // xmm8, xmm9
+       -1,   -1 };
+
+  const unsigned nelts = sizeof(dwarf_64bit) / sizeof(int);
+  int n;
   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
-  if (!Subtarget->is64Bit()) {
-    // Numbers are all different for 32-bit.  Further, some of them
-    // differ between Darwin and other targets.
-    switch (n) {
-    default: assert(0 && "Invalid argument to getDwarfRegNum"); 
-             return n;
-    case 0:  return 0;                              // ax
-    case 1:  return 2;                              // dx
-    case 2:  return 1;                              // cx
-    case 3:  return 3;                              // bx
-    case 4:  return 6;                              // si
-    case 5:  return 7;                              // di
-    case 6:  return (Subtarget->isDarwin) ? 4 : 5;  // bp
-    case 7:  return (Subtarget->isDarwin) ? 5 : 4;  // sp
-
-    case 8:  case 9:  case 10: case 11:             // r8..r15
-    case 12: case 13: case 14: case 15:
-      assert(0 && "Invalid register in 32-bit mode"); 
-      return n;
-
-    case 16: return 8;                              // ip
-
-    case 17: case 18: case 19: case 20:             // xmm0..xmm7  
-    case 21: case 22: case 23: case 24:  
-      return n+4;
-
-    case 25: case 26: case 27: case 28:             // xmm8..xmm15
-    case 29: case 30: case 31: case 32:
-      assert(0 && "Invalid register in 32-bit mode"); 
-      return n;
-
-    case 33: case 34: case 35: case 36:             // st0..st7
-    case 37: case 38: case 39: case 40:
-      return (Subtarget->isDarwin) ? n-21 : n-22;
-
-    case 41: case 42: case 43: case 44:             // mm0..mm7
-    case 45: case 46: case 47: case 48:
-      return n-12;
-    }
+  if (RegNo >= nelts) {
+    assert(0 && "Invalid argument to getDwarfRegNum"); 
+    return -1;
+  }
+  if (Subtarget->is64Bit())
+    n = dwarf_64bit[RegNo];
+  else if (Subtarget->isDarwin)
+    n = dwarf_32bit_darwin[RegNo];
+  else
+    n = dwarf_32bit_linux[RegNo];
+  if (n == -1) {
+    assert(0 && "Invalid register in getDwarfRegNum");
+    return -1;
   }
   return n;
 }
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 4fc23a223f..08f55774c4 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -24,148 +24,146 @@ let Namespace = "X86" in {
   // AL aliases AX if we tell it that AX aliased AL (for example).
 
   // Dwarf numbering is different for 32-bit and 64-bit, and there are
-  // variations by target as well.  The numbers here are for 64-bit.
-  // They are altered by X86RegisterInfo::getDwarfRegNum at runtime.  Note
-  // that we can't assign the same number here to different registers, as
-  // getDwarfRegNum has only the number here to work with.
+  // variations by target as well.  Thus it is not encoded here;
+  // see X86RegisterInfo::getDwarfRegNum.
 
   // 8-bit registers
   // Low registers
-  def AL : Register<"AL">, DwarfRegNum<0>;
-  def DL : Register<"DL">, DwarfRegNum<1>;
-  def CL : Register<"CL">, DwarfRegNum<2>;
-  def BL : Register<"BL">, DwarfRegNum<3>;
+  def AL : Register<"AL">;
+  def DL : Register<"DL">;
+  def CL : Register<"CL">;
+  def BL : Register<"BL">;
 
   // X86-64 only
-  def SIL : Register<"SIL">, DwarfRegNum<4>;
-  def DIL : Register<"DIL">, DwarfRegNum<5>;
-  def BPL : Register<"BPL">, DwarfRegNum<6>;
-  def SPL : Register<"SPL">, DwarfRegNum<7>;
-  def R8B  : Register<"R8B">,  DwarfRegNum<8>;
-  def R9B  : Register<"R9B">,  DwarfRegNum<9>;
-  def R10B : Register<"R10B">, DwarfRegNum<10>;
-  def R11B : Register<"R11B">, DwarfRegNum<11>;
-  def R12B : Register<"R12B">, DwarfRegNum<12>;
-  def R13B : Register<"R13B">, DwarfRegNum<13>;
-  def R14B : Register<"R14B">, DwarfRegNum<14>;
-  def R15B : Register<"R15B">, DwarfRegNum<15>;
+  def SIL : Register<"SIL">;
+  def DIL : Register<"DIL">;
+  def BPL : Register<"BPL">;
+  def SPL : Register<"SPL">;
+  def R8B  : Register<"R8B">;
+  def R9B  : Register<"R9B">;
+  def R10B : Register<"R10B">;
+  def R11B : Register<"R11B">;
+  def R12B : Register<"R12B">;
+  def R13B : Register<"R13B">;
+  def R14B : Register<"R14B">;
+  def R15B : Register<"R15B">;
 
   // High registers X86-32 only
-  def AH : Register<"AH">, DwarfRegNum<0>;
-  def DH : Register<"DH">, DwarfRegNum<1>;
-  def CH : Register<"CH">, DwarfRegNum<2>;
-  def BH : Register<"BH">, DwarfRegNum<3>;
+  def AH : Register<"AH">;
+  def DH : Register<"DH">;
+  def CH : Register<"CH">;
+  def BH : Register<"BH">;
 
   // 16-bit registers
-  def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<0>;
-  def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<1>;
-  def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<2>;
-  def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<3>;
-  def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<4>;
-  def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<5>;
-  def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<6>;
-  def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<7>;
-  def IP : Register<"IP">, DwarfRegNum<16>;
+  def AX : RegisterWithSubRegs<"AX", [AH,AL]>;
+  def DX : RegisterWithSubRegs<"DX", [DH,DL]>;
+  def CX : RegisterWithSubRegs<"CX", [CH,CL]>;
+  def BX : RegisterWithSubRegs<"BX", [BH,BL]>;
+  def SI : RegisterWithSubRegs<"SI", [SIL]>;
+  def DI : RegisterWithSubRegs<"DI", [DIL]>;
+  def BP : RegisterWithSubRegs<"BP", [BPL]>;
+  def SP : RegisterWithSubRegs<"SP", [SPL]>;
+  def IP : Register<"IP">;
   
   // X86-64 only
-  def R8W  : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
-  def R9W  : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<9>;
-  def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<10>;
-  def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<11>;
-  def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<12>;
-  def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<13>;
-  def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<14>;
-  def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<15>;
+  def R8W  : RegisterWithSubRegs<"R8W", [R8B]>;
+  def R9W  : RegisterWithSubRegs<"R9W", [R9B]>;
+  def R10W : RegisterWithSubRegs<"R10W", [R10B]>;
+  def R11W : RegisterWithSubRegs<"R11W", [R11B]>;
+  def R12W : RegisterWithSubRegs<"R12W", [R12B]>;
+  def R13W : RegisterWithSubRegs<"R13W", [R13B]>;
+  def R14W : RegisterWithSubRegs<"R14W", [R14B]>;
+  def R15W : RegisterWithSubRegs<"R15W", [R15B]>;
 
   // 32-bit registers
-  def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<0>;
-  def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<1>;
-  def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<2>;
-  def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<3>;
-  def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<4>;
-  def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<5>;
-  def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<6>;
-  def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<7>;
-  def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<16>;  
+  def EAX : RegisterWithSubRegs<"EAX", [AX]>;
+  def EDX : RegisterWithSubRegs<"EDX", [DX]>;
+  def ECX : RegisterWithSubRegs<"ECX", [CX]>;
+  def EBX : RegisterWithSubRegs<"EBX", [BX]>;
+  def ESI : RegisterWithSubRegs<"ESI", [SI]>;
+  def EDI : RegisterWithSubRegs<"EDI", [DI]>;
+  def EBP : RegisterWithSubRegs<"EBP", [BP]>;
+  def ESP : RegisterWithSubRegs<"ESP", [SP]>;
+  def EIP : RegisterWithSubRegs<"EIP", [IP]>;
   
   // X86-64 only
-  def R8D  : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
-  def R9D  : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<9>;
-  def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<10>;
-  def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<11>;
-  def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<12>;
-  def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<13>;
-  def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<14>;
-  def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<15>;
+  def R8D  : RegisterWithSubRegs<"R8D", [R8W]>;
+  def R9D  : RegisterWithSubRegs<"R9D", [R9W]>;
+  def R10D : RegisterWithSubRegs<"R10D", [R10W]>;
+  def R11D : RegisterWithSubRegs<"R11D", [R11W]>;
+  def R12D : RegisterWithSubRegs<"R12D", [R12W]>;
+  def R13D : RegisterWithSubRegs<"R13D", [R13W]>;
+  def R14D : RegisterWithSubRegs<"R14D", [R14W]>;
+  def R15D : RegisterWithSubRegs<"R15D", [R15W]>;
 
   // 64-bit registers, X86-64 only
-  def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<0>;
-  def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<1>;
-  def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<2>;
-  def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<3>;
-  def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<4>;
-  def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<5>;
-  def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<6>;
-  def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<7>;
-
-  def R8  : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<8>;
-  def R9  : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<9>;
-  def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<10>;
-  def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<11>;
-  def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<12>;
-  def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>;
-  def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>;
-  def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>;
-  def RIP : RegisterWithSubRegs<"RIP", [EIP]>,  DwarfRegNum<16>;
+  def RAX : RegisterWithSubRegs<"RAX", [EAX]>;
+  def RDX : RegisterWithSubRegs<"RDX", [EDX]>;
+  def RCX : RegisterWithSubRegs<"RCX", [ECX]>;
+  def RBX : RegisterWithSubRegs<"RBX", [EBX]>;
+  def RSI : RegisterWithSubRegs<"RSI", [ESI]>;
+  def RDI : RegisterWithSubRegs<"RDI", [EDI]>;
+  def RBP : RegisterWithSubRegs<"RBP", [EBP]>;
+  def RSP : RegisterWithSubRegs<"RSP", [ESP]>;
+
+  def R8  : RegisterWithSubRegs<"R8", [R8D]>;
+  def R9  : RegisterWithSubRegs<"R9", [R9D]>;
+  def R10 : RegisterWithSubRegs<"R10", [R10D]>;
+  def R11 : RegisterWithSubRegs<"R11", [R11D]>;
+  def R12 : RegisterWithSubRegs<"R12", [R12D]>;
+  def R13 : RegisterWithSubRegs<"R13", [R13D]>;
+  def R14 : RegisterWithSubRegs<"R14", [R14D]>;
+  def R15 : RegisterWithSubRegs<"R15", [R15D]>;
+  def RIP : RegisterWithSubRegs<"RIP", [EIP]>;
 
   // MMX Registers. These are actually aliased to ST0 .. ST7
-  def MM0 : Register<"MM0">, DwarfRegNum<41>;
-  def MM1 : Register<"MM1">, DwarfRegNum<42>;
-  def MM2 : Register<"MM2">, DwarfRegNum<43>;
-  def MM3 : Register<"MM3">, DwarfRegNum<44>;
-  def MM4 : Register<"MM4">, DwarfRegNum<45>;
-  def MM5 : Register<"MM5">, DwarfRegNum<46>;
-  def MM6 : Register<"MM6">, DwarfRegNum<47>;
-  def MM7 : Register<"MM7">, DwarfRegNum<48>;
+  def MM0 : Register<"MM0">;
+  def MM1 : Register<"MM1">;
+  def MM2 : Register<"MM2">;
+  def MM3 : Register<"MM3">;
+  def MM4 : Register<"MM4">;
+  def MM5 : Register<"MM5">;
+  def MM6 : Register<"MM6">;
+  def MM7 : Register<"MM7">;
   
   // Pseudo Floating Point registers
-  def FP0 : Register<"FP0">, DwarfRegNum<-1>;
-  def FP1 : Register<"FP1">, DwarfRegNum<-1>;
-  def FP2 : Register<"FP2">, DwarfRegNum<-1>;
-  def FP3 : Register<"FP3">, DwarfRegNum<-1>;
-  def FP4 : Register<"FP4">, DwarfRegNum<-1>;
-  def FP5 : Register<"FP5">, DwarfRegNum<-1>;
-  def FP6 : Register<"FP6">, DwarfRegNum<-1>; 
+  def FP0 : Register<"FP0">;
+  def FP1 : Register<"FP1">;
+  def FP2 : Register<"FP2">;
+  def FP3 : Register<"FP3">;
+  def FP4 : Register<"FP4">;
+  def FP5 : Register<"FP5">;
+  def FP6 : Register<"FP6">;
 
   // XMM Registers, used by the various SSE instruction set extensions
-  def XMM0: Register<"XMM0">, DwarfRegNum<17>;
-  def XMM1: Register<"XMM1">, DwarfRegNum<18>;
-  def XMM2: Register<"XMM2">, DwarfRegNum<19>;
-  def XMM3: Register<"XMM3">, DwarfRegNum<20>;
-  def XMM4: Register<"XMM4">, DwarfRegNum<21>;
-  def XMM5: Register<"XMM5">, DwarfRegNum<22>;
-  def XMM6: Register<"XMM6">, DwarfRegNum<23>;
-  def XMM7: Register<"XMM7">, DwarfRegNum<24>;
+  def XMM0: Register<"XMM0">;
+  def XMM1: Register<"XMM1">;
+  def XMM2: Register<"XMM2">;
+  def XMM3: Register<"XMM3">;
+  def XMM4: Register<"XMM4">;
+  def XMM5: Register<"XMM5">;
+  def XMM6: Register<"XMM6">;
+  def XMM7: Register<"XMM7">;
 
   // X86-64 only
-  def XMM8:  Register<"XMM8">,  DwarfRegNum<25>;
-  def XMM9:  Register<"XMM9">,  DwarfRegNum<26>;
-  def XMM10: Register<"XMM10">, DwarfRegNum<27>;
-  def XMM11: Register<"XMM11">, DwarfRegNum<28>;
-  def XMM12: Register<"XMM12">, DwarfRegNum<29>;
-  def XMM13: Register<"XMM13">, DwarfRegNum<30>;
-  def XMM14: Register<"XMM14">, DwarfRegNum<31>;
-  def XMM15: Register<"XMM15">, DwarfRegNum<32>;
+  def XMM8:  Register<"XMM8">;
+  def XMM9:  Register<"XMM9">;
+  def XMM10: Register<"XMM10">;
+  def XMM11: Register<"XMM11">;
+  def XMM12: Register<"XMM12">;
+  def XMM13: Register<"XMM13">;
+  def XMM14: Register<"XMM14">;
+  def XMM15: Register<"XMM15">;
 
   // Floating point stack registers
-  def ST0 : Register<"ST(0)">, DwarfRegNum<33>;
-  def ST1 : Register<"ST(1)">, DwarfRegNum<34>;
-  def ST2 : Register<"ST(2)">, DwarfRegNum<35>;
-  def ST3 : Register<"ST(3)">, DwarfRegNum<36>;
-  def ST4 : Register<"ST(4)">, DwarfRegNum<37>;
-  def ST5 : Register<"ST(5)">, DwarfRegNum<38>;
-  def ST6 : Register<"ST(6)">, DwarfRegNum<39>;
-  def ST7 : Register<"ST(7)">, DwarfRegNum<40>; 
+  def ST0 : Register<"ST(0)">;
+  def ST1 : Register<"ST(1)">;
+  def ST2 : Register<"ST(2)">;
+  def ST3 : Register<"ST(3)">;
+  def ST4 : Register<"ST(4)">;
+  def ST5 : Register<"ST(5)">;
+  def ST6 : Register<"ST(6)">;
+  def ST7 : Register<"ST(7)">;
 
   // Status flags register
   def EFLAGS : Register<"EFLAGS">;