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| author | Cameron McInally <cameron.mcinally@nyu.edu> | 2014-02-19 15:16:09 +0000 |
|---|---|---|
| committer | Cameron McInally <cameron.mcinally@nyu.edu> | 2014-02-19 15:16:09 +0000 |
| commit | 35f15e54a91652738d7d3fd858e0389001d3d806 (patch) | |
| tree | 8ccf641b57d94ab4f369bb4f13234d291806cc32 | |
| parent | 6e2c745e992c0aab1a1eeda7c3cf279a591e1b94 (diff) | |
| download | llvm-35f15e54a91652738d7d3fd858e0389001d3d806.tar.gz llvm-35f15e54a91652738d7d3fd858e0389001d3d806.tar.bz2 llvm-35f15e54a91652738d7d3fd858e0389001d3d806.tar.xz | |
Fix AVX512 vector sqrt assembly strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201681 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrAVX512.td | 8 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx512-arith.ll | 18 |
2 files changed, 22 insertions, 4 deletions
diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index f6a5a25a54..3b19410ac7 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -3275,25 +3275,25 @@ multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode, Intrinsic V16F32Int, Intrinsic V8F64Int, OpndItins itins_s, OpndItins itins_d> { def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), - !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), + !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>, EVEX, EVEX_V512; let mayLoad = 1 in def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src), - !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), + !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), [(set VR512:$dst, (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))], itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>; def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), - !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), + !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>, EVEX, EVEX_V512; let mayLoad = 1 in def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src), - !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), + !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), [(set VR512:$dst, (OpNode (v8f64 (bitconvert (memopv16f32 addr:$src)))))], itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>; diff --git a/test/CodeGen/X86/avx512-arith.ll b/test/CodeGen/X86/avx512-arith.ll index 223c023a8a..3966552e95 100644 --- a/test/CodeGen/X86/avx512-arith.ll +++ b/test/CodeGen/X86/avx512-arith.ll @@ -224,6 +224,24 @@ define float @sqrtC(float %a) nounwind { ret float %b } +; CHECK-LABEL: sqrtD +; CHECK: vsqrtps {{.*}} +; CHECK: ret +declare <16 x float> @llvm.sqrt.v16f32(<16 x float>) +define <16 x float> @sqrtD(<16 x float> %a) nounwind { + %b = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a) + ret <16 x float> %b +} + +; CHECK-LABEL: sqrtE +; CHECK: vsqrtpd {{.*}} +; CHECK: ret +declare <8 x double> @llvm.sqrt.v8f64(<8 x double>) +define <8 x double> @sqrtE(<8 x double> %a) nounwind { + %b = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a) + ret <8 x double> %b +} + ; CHECK-LABEL: fadd_broadcast ; CHECK: LCP{{.*}}(%rip){1to16}, %zmm0, %zmm0 ; CHECK: ret |