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authorAkira Hatanaka <ahatanaka@mips.com>2012-11-03 00:26:02 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-11-03 00:26:02 +0000
commit3c9c1ab7b7549dfaf22456d89bd241a5e8dfc0a4 (patch)
treefb7b5638a6eb37c0b6dfc0626e7588cbc0632532
parentefcc1aec6459c356c6516e28be29acaa51e876fa (diff)
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[mips] Set flag isAsCheapAsAMove flag on instruction LUi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167345 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Mips/MipsInstrInfo.td2
-rw-r--r--test/CodeGen/Mips/remat-immed-load.ll25
2 files changed, 26 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 3f6cebdc18..3319553935 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -421,7 +421,7 @@ class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
// Load Upper Imediate
class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
FI<op, (outs RC:$rt), (ins Imm:$imm16),
- !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
+ !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove {
let rs = 0;
let neverHasSideEffects = 1;
let isReMaterializable = 1;
diff --git a/test/CodeGen/Mips/remat-immed-load.ll b/test/CodeGen/Mips/remat-immed-load.ll
index e4548f8ce2..d93964bcae 100644
--- a/test/CodeGen/Mips/remat-immed-load.ll
+++ b/test/CodeGen/Mips/remat-immed-load.ll
@@ -24,3 +24,28 @@ entry:
}
declare void @foo2(i64)
+
+define void @f5() nounwind {
+entry:
+; 32: lui $4, 1
+; 32: lui $4, 1
+
+ tail call void @f6(i32 65536) nounwind
+ tail call void @f6(i32 65536) nounwind
+ ret void
+}
+
+declare void @f6(i32)
+
+define void @f7() nounwind {
+entry:
+; 64: lui $4, 1
+; 64: lui $4, 1
+
+ tail call void @f8(i64 65536) nounwind
+ tail call void @f8(i64 65536) nounwind
+ ret void
+}
+
+declare void @f8(i64)
+