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authorJim Grosbach <grosbach@apple.com>2010-09-02 18:44:51 +0000
committerJim Grosbach <grosbach@apple.com>2010-09-02 18:44:51 +0000
commit3e234e757965a3c30f31227b60575841441368b6 (patch)
treed990b2cddf028f208a6847e2d590c91ebb662ccd
parent6b1d0a3b366a637c0c96ea5cf7cfd8769469e6f3 (diff)
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remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112847 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/TargetRegisterInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp
index 6addbab851..55f222c7c1 100644
--- a/lib/Target/TargetRegisterInfo.cpp
+++ b/lib/Target/TargetRegisterInfo.cpp
@@ -63,7 +63,7 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
/// getAllocatableSetForRC - Toggle the bits that represent allocatable
/// registers for the specific register class.
static void getAllocatableSetForRC(const MachineFunction &MF,
- const TargetRegisterClass *RC, BitVector &R){
+ const TargetRegisterClass *RC, BitVector &R){
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I)
R.set(*I);