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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-01 13:10:16 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-01 13:10:16 +0000 |
| commit | 47086570973e82fe5ea8ace9637ae73c2469e1da (patch) | |
| tree | 53ca5b89f45584cd94882d0060ec66e735faa2e4 | |
| parent | 4c8feae136bbb54ba09d8f8dc7e61714270f7cd5 (diff) | |
| download | llvm-47086570973e82fe5ea8ace9637ae73c2469e1da.tar.gz llvm-47086570973e82fe5ea8ace9637ae73c2469e1da.tar.bz2 llvm-47086570973e82fe5ea8ace9637ae73c2469e1da.tar.xz | |
[SystemZ] Allow selects with a high-word destination
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191751 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/SystemZ/SystemZISelLowering.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 5 | ||||
| -rw-r--r-- | test/CodeGen/SystemZ/asm-18.ll | 28 |
3 files changed, 32 insertions, 2 deletions
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index cb0f445cf7..46824e60fc 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -2874,6 +2874,7 @@ SystemZTargetLowering::emitStringWrapper(MachineInstr *MI, MachineBasicBlock *SystemZTargetLowering:: EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const { switch (MI->getOpcode()) { + case SystemZ::Select32Mux: case SystemZ::Select32: case SystemZ::SelectF32: case SystemZ::Select64: diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 00229260f6..ac1ca3ce18 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -198,8 +198,9 @@ let Defs = [CC] in { // Select instructions //===----------------------------------------------------------------------===// -def Select32 : SelectWrapper<GR32>; -def Select64 : SelectWrapper<GR64>; +def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>; +def Select32 : SelectWrapper<GR32>; +def Select64 : SelectWrapper<GR64>; defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, nonvolatile_anyextloadi8, bdxaddr20only>; diff --git a/test/CodeGen/SystemZ/asm-18.ll b/test/CodeGen/SystemZ/asm-18.ll index e7e171e80b..6126b50c17 100644 --- a/test/CodeGen/SystemZ/asm-18.ll +++ b/test/CodeGen/SystemZ/asm-18.ll @@ -287,3 +287,31 @@ define void @f12() { i32 1000000000, i32 400000) ret void } + +; Test selects involving high registers. +define void @f13(i32 %x, i32 %y) { +; CHECK-LABEL: f13: +; CHECK: llihl [[REG:%r[0-5]]], 0 +; CHECK: cije %r2, 0 +; CHECK: iihf [[REG]], 2102030405 +; CHECK: blah [[REG]] +; CHECK: br %r14 + %cmp = icmp eq i32 %x, 0 + %val = select i1 %cmp, i32 0, i32 2102030405 + call void asm sideeffect "blah $0", "h"(i32 %val) + ret void +} + +; Test selects involving low registers. +define void @f14(i32 %x, i32 %y) { +; CHECK-LABEL: f14: +; CHECK: lhi [[REG:%r[0-5]]], 0 +; CHECK: cije %r2, 0 +; CHECK: iilf [[REG]], 2102030405 +; CHECK: blah [[REG]] +; CHECK: br %r14 + %cmp = icmp eq i32 %x, 0 + %val = select i1 %cmp, i32 0, i32 2102030405 + call void asm sideeffect "blah $0", "r"(i32 %val) + ret void +} |