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author | Johnny Chen <johnny.chen@apple.com> | 2011-04-13 21:04:32 +0000 |
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committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-13 21:04:32 +0000 |
commit | 471d73d5d387d52dc854145caca971dfd9fd506a (patch) | |
tree | 169b06d6d1be747e727f372e1b49b177c1aa835d | |
parent | 5af60ce2a8d4dc820664c9dc5fbbcff428402c15 (diff) | |
download | llvm-471d73d5d387d52dc854145caca971dfd9fd506a.tar.gz llvm-471d73d5d387d52dc854145caca971dfd9fd506a.tar.bz2 llvm-471d73d5d387d52dc854145caca971dfd9fd506a.tar.xz |
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
rdar://problem/9279440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 4 | ||||
-rw-r--r-- | lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 20 | ||||
-rw-r--r-- | test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt | 10 |
3 files changed, 26 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 5c13d83db3..2f4198ba8e 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1381,7 +1381,7 @@ def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn), // for disassembly only. // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> - : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, + : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, "\t$Rt, $addr", []> { let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; @@ -1472,7 +1472,7 @@ def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb), // only. // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 class T2IstT<bits<2> type, string opc, InstrItinClass ii> - : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, + : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, "\t$Rt, $addr", []> { let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index 71451e3e2e..ec8005627e 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1909,6 +1909,8 @@ static bool BadRegsThumb2LdSt(unsigned Opcode, uint32_t insn, bool Load, // Inst{22-21} encodes the data item transferred for load/store. // For single word, it is encoded as ob10. bool Word = (slice(insn, 22, 21) == 2); + bool Half = (slice(insn, 22, 21) == 1); + bool Byte = (slice(insn, 22, 21) == 0); if (UseRm && BadReg(R2)) { DEBUG(errs() << "if BadReg(m) then UNPREDICTABLE\n"); @@ -1920,9 +1922,15 @@ static bool BadRegsThumb2LdSt(unsigned Opcode, uint32_t insn, bool Load, DEBUG(errs() << "if t == 13 then UNPREDICTABLE\n"); return true; } + if (Byte) { + if (WB && R0 == 15 && slice(insn, 10, 8) == 3) { + // A8.6.78 LDRSB (immediate) Encoding T2 (errata markup 8.0) + DEBUG(errs() << "if t == 15 && PUW == '011' then UNPREDICTABLE\n"); + return true; + } + } // A6.3.8 Load halfword, memory hints - const StringRef Name = ARMInsts[Opcode].Name; - if (Name.startswith("t2LDRH") || Name.startswith("t2LDRSH")) { + if (Half) { if (WB) { if (R0 == R1) { // A8.6.82 LDRSH (immediate) Encoding T2 @@ -2021,8 +2029,8 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode, OpIdx = 0; assert(NumOps >= 3 && - OpInfo[0].RegClass == ARM::GPRRegClassID && - OpInfo[1].RegClass == ARM::GPRRegClassID && + OpInfo[0].RegClass > 0 && + OpInfo[1].RegClass > 0 && "Expect >= 3 operands and first two as reg operands"); bool ThreeReg = (OpInfo[2].RegClass > 0); @@ -2061,10 +2069,10 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode, Imm = decodeImm8(insn); } - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass, R0))); ++OpIdx; - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass, R1))); ++OpIdx; diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt new file mode 100644 index 0000000000..9befbd6b6f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# The unpriviledged Load/Store cannot have SP or PC as Rt. +0x10 0xf8 0x3 0xfe |