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authorSasa Stankovic <Sasa.Stankovic@imgtec.com>2014-06-09 14:09:28 +0000
committerSasa Stankovic <Sasa.Stankovic@imgtec.com>2014-06-09 14:09:28 +0000
commit49b83e1e7683358de784657c74d838d64f773dba (patch)
treed487cbe439338a4355600423f584d8cfc814f97b
parent592d439efee50c81b44285ea718c881281320ce0 (diff)
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[mips] Fix a bug for NaCl target - Don't report the error when non-dangerous
load/store is in branch delay slot. Differential Revision: http://llvm-reviews.chandlerc.com/D4048 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210470 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp13
-rw-r--r--test/MC/Mips/nacl-mask.s34
2 files changed, 40 insertions, 7 deletions
diff --git a/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
index cd6be734df..9a7fc85e91 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
@@ -137,18 +137,17 @@ public:
&IsStore);
bool IsSPFirstOperand = isStackPointerFirstOperand(Inst);
if (IsMemAccess || IsSPFirstOperand) {
- if (PendingCall)
- report_fatal_error("Dangerous instruction in branch delay slot!");
-
bool MaskBefore = (IsMemAccess
&& baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
.getReg()));
bool MaskAfter = IsSPFirstOperand && !IsStore;
- if (MaskBefore || MaskAfter)
+ if (MaskBefore || MaskAfter) {
+ if (PendingCall)
+ report_fatal_error("Dangerous instruction in branch delay slot!");
sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
- else
- MipsELFStreamer::EmitInstruction(Inst, STI);
- return;
+ return;
+ }
+ // fallthrough
}
// Sandbox calls by aligning call and branch delay to the bundle end.
diff --git a/test/MC/Mips/nacl-mask.s b/test/MC/Mips/nacl-mask.s
index 820583549c..22286ac7db 100644
--- a/test/MC/Mips/nacl-mask.s
+++ b/test/MC/Mips/nacl-mask.s
@@ -283,3 +283,37 @@ test5:
# CHECK-NEXT: and $25, $25, $14
# CHECK-NEXT: jalr $25
# CHECK-NEXT: addiu $4, $zero, 5
+
+
+
+# Test that we can put non-dangerous loads and stores in branch delay slot.
+
+ .align 4
+test6:
+ .set noreorder
+
+ jal func1
+ sw $4, 0($sp)
+
+ bal func2
+ lw $5, 0($t8)
+
+ jalr $t9
+ sw $sp, 0($sp)
+
+# CHECK-LABEL: test6:
+
+# CHECK-NEXT: nop
+# CHECK-NEXT: nop
+# CHECK-NEXT: jal
+# CHECK-NEXT: sw $4, 0($sp)
+
+# CHECK-NEXT: nop
+# CHECK-NEXT: nop
+# CHECK-NEXT: bal
+# CHECK-NEXT: lw $5, 0($24)
+
+# CHECK-NEXT: nop
+# CHECK-NEXT: and $25, $25, $14
+# CHECK-NEXT: jalr
+# CHECK-NEXT: sw $sp, 0($sp)