Use TRI::printReg instead of AbstractRegisterDescription when printing

LiveIntervalUnions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 13 insertions, 34 deletions

diff --git a/lib/CodeGen/LiveIntervalUnion.cpp b/lib/CodeGen/LiveIntervalUnion.cpp
index 59d48a4b64..e8b39914ca 100644
--- a/lib/CodeGen/LiveIntervalUnion.cpp
+++ b/lib/CodeGen/LiveIntervalUnion.cpp
@@ -18,7 +18,10 @@
 #include "llvm/ADT/SparseBitVector.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+
 #include <algorithm>
+
 using namespace llvm;
 
 
@@ -66,24 +69,16 @@ void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
 }
 
 void
-LiveIntervalUnion::print(raw_ostream &OS,
-                         const AbstractRegisterDescription *RegDesc) const {
+LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
   OS << "LIU ";
-  if (RegDesc != NULL)
-    OS << RegDesc->getName(RepReg);
-  else {
-    OS << RepReg;
+  TRI->printReg(RepReg, OS);
+  for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
+    OS << " [" << SI.start() << ' ' << SI.stop() << "):";
+    TRI->printReg(SI.value()->reg, OS);
   }
-  for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI)
-    dbgs() << " [" << SI.start() << ' ' << SI.stop() << "):%reg"
-           << SI.value()->reg;
   OS << "\n";
 }
 
-void LiveIntervalUnion::dump(const AbstractRegisterDescription *RegDesc) const {
-  print(dbgs(), RegDesc);
-}
-
 #ifndef NDEBUG
 // Verify the live intervals in this union and add them to the visited set.
 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
diff --git a/lib/CodeGen/LiveIntervalUnion.h b/lib/CodeGen/LiveIntervalUnion.h
index 5bf86d8c02..92d248266e 100644
--- a/lib/CodeGen/LiveIntervalUnion.h
+++ b/lib/CodeGen/LiveIntervalUnion.h
@@ -22,19 +22,14 @@
 
 namespace llvm {
 
+class TargetRegisterInfo;
+
 #ifndef NDEBUG
 // forward declaration
 template <unsigned Element> class SparseBitVector;
 typedef SparseBitVector<128> LiveVirtRegBitSet;
 #endif
 
-/// Abstraction to provide info for the representative register.
-class AbstractRegisterDescription {
-public:
-  virtual const char *getName(unsigned Reg) const = 0;
-  virtual ~AbstractRegisterDescription() {}
-};
-
 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
 inline bool
 overlap(const LiveRange &VRSeg,
@@ -85,10 +80,8 @@ public:
   // Remove a live virtual register's segments from this union.
   void extract(LiveInterval &VirtReg);
 
-  void dump(const AbstractRegisterDescription *RegDesc) const;
-
-  // If tri != NULL, use it to decode RepReg
-  void print(raw_ostream &OS, const AbstractRegisterDescription *RegDesc) const;
+  // Print union, using TRI to translate register names
+  void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
 
 #ifndef NDEBUG
   // Verify the live intervals in this union and add them to the visited set.
diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp
index eb1b9075b3..a5e5f1f308 100644
--- a/lib/CodeGen/RegAllocBasic.cpp
+++ b/lib/CodeGen/RegAllocBasic.cpp
@@ -60,14 +60,6 @@ VerifyRegAlloc("verify-regalloc",
 const char *RegAllocBase::TimerGroupName = "Register Allocation";
 
 namespace {
-
-class PhysicalRegisterDescription : public AbstractRegisterDescription {
-  const TargetRegisterInfo *TRI;
-public:
-  PhysicalRegisterDescription(const TargetRegisterInfo *T): TRI(T) {}
-  virtual const char *getName(unsigned Reg) const { return TRI->getName(Reg); }
-};
-
 /// RABasic provides a minimal implementation of the basic register allocation
 /// algorithm. It prioritizes live virtual registers by spill weight and spills
 /// whenever a register is unavailable. This is not practical in production but
@@ -165,8 +157,7 @@ void RegAllocBase::verify() {
 
   // Verify disjoint unions.
   for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
-    DEBUG(PhysicalRegisterDescription PRD(TRI);
-          PhysReg2LiveUnion[PhysReg].dump(&PRD));
+    DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
     LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
     PhysReg2LiveUnion[PhysReg].verify(VRegs);
     // Union + intersection test could be done efficiently in one pass, but