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authorRichard Osborne <richard@xmos.com>2011-01-31 17:41:44 +0000
committerRichard Osborne <richard@xmos.com>2011-01-31 17:41:44 +0000
commit4e3740ee6ddfc5895061245364de21e3f73517fe (patch)
treef6c7135d55a72babcac2a2f2a4b920878d39cb40
parente85dcb54d1a2bb957a430212b1f2b1c88553878a (diff)
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Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp4
-rw-r--r--test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll10
2 files changed, 12 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 94487d4041..e91592b242 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4244,8 +4244,6 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
if (Opc == ISD::SIGN_EXTEND_INREG) {
ExtType = ISD::SEXTLOAD;
ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
- if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
- return SDValue();
} else if (Opc == ISD::SRL) {
// Another special-case: SRL is basically zero-extending a narrower value.
ExtType = ISD::ZEXTLOAD;
@@ -4255,6 +4253,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
ExtVT = EVT::getIntegerVT(*DAG.getContext(),
VT.getSizeInBits() - N01->getZExtValue());
}
+ if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
+ return SDValue();
unsigned EVTBits = ExtVT.getSizeInBits();
diff --git a/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll b/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
new file mode 100644
index 0000000000..f8fe0d2136
--- /dev/null
+++ b/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=xcore
+%struct.st = type <{ i8, i32, i8, i32, i8, i32 }>
+
+@x = external global %struct.st, align 4
+
+define i32 @test_entry() nounwind {
+entry:
+ %0 = load i32* getelementptr inbounds (%struct.st* @x, i32 0, i32 3), align 2
+ ret i32 %0
+}