diff options
| author | Weiming Zhao <weimingz@codeaurora.org> | 2013-12-18 22:25:17 +0000 |
|---|---|---|
| committer | Weiming Zhao <weimingz@codeaurora.org> | 2013-12-18 22:25:17 +0000 |
| commit | 4fdb649f3aa05e7b25dab499af39d623e84acafe (patch) | |
| tree | d7cdf09e73d8c4da5ea76ecfd3354fde7baed7b4 | |
| parent | 5112542840c5be96f2245a2a0fa59dea57dfe6f4 (diff) | |
| download | llvm-4fdb649f3aa05e7b25dab499af39d623e84acafe.tar.gz llvm-4fdb649f3aa05e7b25dab499af39d623e84acafe.tar.bz2 llvm-4fdb649f3aa05e7b25dab499af39d623e84acafe.tar.xz | |
[aarch32] fix bug 18268: Incorrect condition of vsel
Given vsel_cc, op1, op2, since vsel has no LE/LT, to generate vsel for
such selection, it needs to inverse cc and swap op1 and op2. To inverse
cc, both L/G and E bits should be flipped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197615 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vsel.ll | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 9bdec10a64..017c86667e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -3232,7 +3232,7 @@ SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) { if (CC == ISD::SETNE) return ISD::SETEQ; - return ISD::getSetCCSwappedOperands(CC); + return ISD::getSetCCInverse(CC, true); } static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, diff --git a/test/CodeGen/ARM/vsel.ll b/test/CodeGen/ARM/vsel.ll index 7e1f7146fd..746b1b000e 100644 --- a/test/CodeGen/ARM/vsel.ll +++ b/test/CodeGen/ARM/vsel.ll @@ -61,7 +61,7 @@ define void @test_vsel32slt(i32 %lhs32, i32 %rhs32, float %a, float %b) { %val1 = select i1 %tst1, float %a, float %b store float %val1, float* @varfloat ; CHECK: cmp r0, r1 -; CHECK: vselgt.f32 s0, s1, s0 +; CHECK: vselge.f32 s0, s1, s0 ret void } define void @test_vsel64slt(i32 %lhs32, i32 %rhs32, double %a, double %b) { @@ -70,7 +70,7 @@ define void @test_vsel64slt(i32 %lhs32, i32 %rhs32, double %a, double %b) { %val1 = select i1 %tst1, double %a, double %b store double %val1, double* @vardouble ; CHECK: cmp r0, r1 -; CHECK: vselgt.f64 d16, d1, d0 +; CHECK: vselge.f64 d16, d1, d0 ret void } define void @test_vsel32sle(i32 %lhs32, i32 %rhs32, float %a, float %b) { @@ -79,7 +79,7 @@ define void @test_vsel32sle(i32 %lhs32, i32 %rhs32, float %a, float %b) { %val1 = select i1 %tst1, float %a, float %b store float %val1, float* @varfloat ; CHECK: cmp r0, r1 -; CHECK: vselge.f32 s0, s1, s0 +; CHECK: vselgt.f32 s0, s1, s0 ret void } define void @test_vsel64sle(i32 %lhs32, i32 %rhs32, double %a, double %b) { @@ -88,7 +88,7 @@ define void @test_vsel64sle(i32 %lhs32, i32 %rhs32, double %a, double %b) { %val1 = select i1 %tst1, double %a, double %b store double %val1, double* @vardouble ; CHECK: cmp r0, r1 -; CHECK: vselge.f64 d16, d1, d0 +; CHECK: vselgt.f64 d16, d1, d0 ret void } define void @test_vsel32ogt(float %lhs32, float %rhs32, float %a, float %b) { |