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author | Nadav Rotem <nadav.rotem@intel.com> | 2011-09-12 08:41:50 +0000 |
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committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-09-12 08:41:50 +0000 |
commit | 5ed098320029cfa6d26a46a13f333588aa18b6a7 (patch) | |
tree | b670031ed0dbb16462033aac0e1559fce3c0a8c4 | |
parent | 136046c9a2dcb9b5bf539e6c6fcf100c68f9e621 (diff) | |
download | llvm-5ed098320029cfa6d26a46a13f333588aa18b6a7.tar.gz llvm-5ed098320029cfa6d26a46a13f333588aa18b6a7.tar.bz2 llvm-5ed098320029cfa6d26a46a13f333588aa18b6a7.tar.xz |
Format patterns, remove unused X86blend patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139491 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86InstrFragmentsSIMD.td | 3 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 58 |
2 files changed, 34 insertions, 27 deletions
diff --git a/lib/Target/X86/X86InstrFragmentsSIMD.td b/lib/Target/X86/X86InstrFragmentsSIMD.td index f25435f85e..aa088a62c4 100644 --- a/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -58,9 +58,6 @@ def X86psignw : SDNode<"X86ISD::PSIGNW", def X86psignd : SDNode<"X86ISD::PSIGND", SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; -def X86blendv : SDNode<"X86ISD::BLENDV", - SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, - SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>; def X86pextrb : SDNode<"X86ISD::PEXTRB", SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; def X86pextrw : SDNode<"X86ISD::PEXTRW", diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index c5020e7428..25ee19158c 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -5930,27 +5930,34 @@ defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem, memopv32i8, int_x86_avx_blendv_ps_256>; let Predicates = [HasAVX] in { -def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), - VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1), - (v16i8 VR128:$src2))), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v16i8 VR128:$src2))), + (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1), - (v4i32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v4i32 VR128:$src2))), + (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1), - (v4f32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v4f32 VR128:$src2))), + (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1), - (v2i64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v2i64 VR128:$src2))), + (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1), - (v2f64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v2f64 VR128:$src2))), + (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1), - (v8i32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (v8i32 VR256:$src2))), + (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1), - (v8f32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (v8f32 VR256:$src2))), + (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1), - (v4i64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (v4i64 VR256:$src2))), + (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1), - (v4f64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (v4f64 VR256:$src2))), + (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; } @@ -5979,19 +5986,22 @@ defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>; defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>; let Predicates = [HasSSE41] in { -def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), - VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; - - def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1), - (v16i8 VR128:$src2))), (PBLENDVBrr0 VR128:$src1, VR128:$src2)>; - def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1), - (v4i32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; - def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1), - (v4f32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; - def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1), - (v2i64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; - def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), - (v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; + +def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1), + (v16i8 VR128:$src2))), + (PBLENDVBrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1), + (v4i32 VR128:$src2))), + (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1), + (v4f32 VR128:$src2))), + (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1), + (v2i64 VR128:$src2))), + (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), + (v2f64 VR128:$src2))), + (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; } let Predicates = [HasAVX] in |