diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-11-28 06:05:59 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-11-28 06:05:59 +0000 |
| commit | 680cd7b07707407ff29083b2fcad97c076213b8c (patch) | |
| tree | 36dc7306a989ef40a140b7beb2c86047a8541bbb | |
| parent | 91e710c3dd955e80a4d0fc3a7c26c115b61f8556 (diff) | |
| download | llvm-680cd7b07707407ff29083b2fcad97c076213b8c.tar.gz llvm-680cd7b07707407ff29083b2fcad97c076213b8c.tar.bz2 llvm-680cd7b07707407ff29083b2fcad97c076213b8c.tar.xz | |
Don't share functional units among the PPC itineraries
Instead of sharing functional unit names between the various PPC itineraries,
give each core its own unit names prefixed with the core name. This follows
the convention used by other backends (such as ARM), and removes a non-obvious
ordering dependency between the various PPCSchedule*.td files.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195908 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCSchedule.td | 15 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCSchedule440.td | 1087 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleA2.td | 118 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleE500mc.td | 369 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleE5500.td | 439 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG3.td | 116 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4.td | 144 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4Plus.td | 164 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG5.td | 173 |
9 files changed, 1364 insertions, 1261 deletions
diff --git a/lib/Target/PowerPC/PPCSchedule.td b/lib/Target/PowerPC/PPCSchedule.td index 45dcb23fbc..452db1581d 100644 --- a/lib/Target/PowerPC/PPCSchedule.td +++ b/lib/Target/PowerPC/PPCSchedule.td @@ -8,21 +8,6 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Functional units across PowerPC chips sets -// -def BPU : FuncUnit; // Branch unit -def SLU : FuncUnit; // Store/load unit -def SRU : FuncUnit; // special register unit -def IU1 : FuncUnit; // integer unit 1 (simple) -def IU2 : FuncUnit; // integer unit 2 (complex) -def FPU1 : FuncUnit; // floating point unit 1 -def FPU2 : FuncUnit; // floating point unit 2 -def VPU : FuncUnit; // vector permutation unit -def VIU1 : FuncUnit; // vector integer unit 1 (simple) -def VIU2 : FuncUnit; // vector integer unit 2 (complex) -def VFPU : FuncUnit; // vector floating point unit - -//===----------------------------------------------------------------------===// // Instruction Itinerary classes used for PowerPC // def IIC_IntSimple : InstrItinClass; diff --git a/lib/Target/PowerPC/PPCSchedule440.td b/lib/Target/PowerPC/PPCSchedule440.td index 9137720783..c52819d70c 100644 --- a/lib/Target/PowerPC/PPCSchedule440.td +++ b/lib/Target/PowerPC/PPCSchedule440.td @@ -26,43 +26,43 @@ //===----------------------------------------------------------------------===// // Functional units on the PowerPC 440/450 chip sets // -def IFTH1 : FuncUnit; // Fetch unit 1 -def IFTH2 : FuncUnit; // Fetch unit 2 -def PDCD1 : FuncUnit; // Decode unit 1 -def PDCD2 : FuncUnit; // Decode unit 2 -def DISS1 : FuncUnit; // Issue unit 1 -def DISS2 : FuncUnit; // Issue unit 2 -def LRACC : FuncUnit; // Register access and dispatch for - // the simple integer (J-pipe) and - // load/store (L-pipe) pipelines -def IRACC : FuncUnit; // Register access and dispatch for - // the complex integer (I-pipe) pipeline -def FRACC : FuncUnit; // Register access and dispatch for - // the floating-point execution (F-pipe) pipeline -def IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline -def IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline -def IWB : FuncUnit; // Write-back unit for the I pipeline -def JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline -def JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline -def JWB : FuncUnit; // Write-back unit for the J pipeline -def AGEN : FuncUnit; // Address generation for the L pipeline -def CRD : FuncUnit; // D-cache access for the L pipeline -def LWB : FuncUnit; // Write-back unit for the L pipeline -def FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline -def FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline -def FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline -def FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline -def FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline -def FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline -def FWB : FuncUnit; // Write-back unit for the F pipeline +def P440_IFTH1 : FuncUnit; // Fetch unit 1 +def P440_IFTH2 : FuncUnit; // Fetch unit 2 +def P440_PDCD1 : FuncUnit; // Decode unit 1 +def P440_PDCD2 : FuncUnit; // Decode unit 2 +def P440_DISS1 : FuncUnit; // Issue unit 1 +def P440_DISS2 : FuncUnit; // Issue unit 2 +def P440_LRACC : FuncUnit; // Register access and dispatch for + // the simple integer (J-pipe) and + // load/store (L-pipe) pipelines +def P440_IRACC : FuncUnit; // Register access and dispatch for + // the complex integer (I-pipe) pipeline +def P440_FRACC : FuncUnit; // Register access and dispatch for + // the floating-point execution (F-pipe) pipeline +def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline +def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline +def P440_IWB : FuncUnit; // Write-back unit for the I pipeline +def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline +def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline +def P440_JWB : FuncUnit; // Write-back unit for the J pipeline +def P440_AGEN : FuncUnit; // Address generation for the L pipeline +def P440_CRD : FuncUnit; // D-cache access for the L pipeline +def P440_LWB : FuncUnit; // Write-back unit for the L pipeline +def P440_FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline +def P440_FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline +def P440_FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline +def P440_FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline +def P440_FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline +def P440_FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline +def P440_FWB : FuncUnit; // Write-back unit for the F pipeline -def LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used - // to make sure that no lwarx/stwcx. - // instructions are issued while another - // lwarx/stwcx. is in the L pipe. +def P440_LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used + // to make sure that no lwarx/stwcx. + // instructions are issued while another + // lwarx/stwcx. is in the L pipe. -def GPR_Bypass : Bypass; // The bypass for general-purpose regs. -def FPR_Bypass : Bypass; // The bypass for floating-point regs. +def P440_GPR_Bypass : Bypass; // The bypass for general-purpose regs. +def P440_FPR_Bypass : Bypass; // The bypass for floating-point regs. // Notes: // Instructions are held in the FRACC, LRACC and IRACC pipeline @@ -104,560 +104,573 @@ def FPR_Bypass : Bypass; // The bypass for floating-point regs. def PPC440Itineraries : ProcessorItineraries< - [IFTH1, IFTH2, PDCD1, PDCD2, DISS1, DISS2, FRACC, - IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB, - FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold], - [GPR_Bypass, FPR_Bypass], [ - InstrItinData<IIC_IntSimple, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC, LRACC]>, - InstrStage<1, [IEXE1, JEXE1]>, - InstrStage<1, [IEXE2, JEXE2]>, - InstrStage<1, [IWB, JWB]>], + [P440_IFTH1, P440_IFTH2, P440_PDCD1, P440_PDCD2, P440_DISS1, P440_DISS2, + P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2, P440_IWB, P440_LRACC, + P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD, P440_LWB, P440_FEXE1, + P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5, P440_FEXE6, P440_FWB, + P440_LWARX_Hold], + [P440_GPR_Bypass, P440_FPR_Bypass], [ + InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC, P440_LRACC]>, + InstrStage<1, [P440_IEXE1, P440_JEXE1]>, + InstrStage<1, [P440_IEXE2, P440_JEXE2]>, + InstrStage<1, [P440_IWB, P440_JWB]>], [6, 4, 4], - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntGeneral, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC, LRACC]>, - InstrStage<1, [IEXE1, JEXE1]>, - InstrStage<1, [IEXE2, JEXE2]>, - InstrStage<1, [IWB, JWB]>], + [P440_GPR_Bypass, + P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC, P440_LRACC]>, + InstrStage<1, [P440_IEXE1, P440_JEXE1]>, + InstrStage<1, [P440_IEXE2, P440_JEXE2]>, + InstrStage<1, [P440_IWB, P440_JWB]>], [6, 4, 4], - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntCompare, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC, LRACC]>, - InstrStage<1, [IEXE1, JEXE1]>, - InstrStage<1, [IEXE2, JEXE2]>, - InstrStage<1, [IWB, JWB]>], + [P440_GPR_Bypass, + P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC, P440_LRACC]>, + InstrStage<1, [P440_IEXE1, P440_JEXE1]>, + InstrStage<1, [P440_IEXE2, P440_JEXE2]>, + InstrStage<1, [P440_IWB, P440_JWB]>], [6, 4, 4], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntDivW, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<33, [IWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<33, [P440_IWB]>], [40, 4, 4], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMFFS, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [7, 4, 4], - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [P440_GPR_Bypass, + P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [7, 4, 4], - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMulHW, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [P440_GPR_Bypass, + P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4, 4], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMulHWU, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4, 4], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMulLI, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4, 4], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntRotate, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC, LRACC]>, - InstrStage<1, [IEXE1, JEXE1]>, - InstrStage<1, [IEXE2, JEXE2]>, - InstrStage<1, [IWB, JWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC, P440_LRACC]>, + InstrStage<1, [P440_IEXE1, P440_JEXE1]>, + InstrStage<1, [P440_IEXE2, P440_JEXE2]>, + InstrStage<1, [P440_IWB, P440_JWB]>], [6, 4, 4], - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntShift, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC, LRACC]>, - InstrStage<1, [IEXE1, JEXE1]>, - InstrStage<1, [IEXE2, JEXE2]>, - InstrStage<1, [IWB, JWB]>], + [P440_GPR_Bypass, + P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntShift, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC, P440_LRACC]>, + InstrStage<1, [P440_IEXE1, P440_JEXE1]>, + InstrStage<1, [P440_IEXE2, P440_JEXE2]>, + InstrStage<1, [P440_IWB, P440_JWB]>], [6, 4, 4], - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntTrapW, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [P440_GPR_Bypass, + P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [6, 4], - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_BrB, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_BrB, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_BrCR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_BrCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4, 4], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_BrMCR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4, 4], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_BrMCRX, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4, 4], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBA, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBF, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBI, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLoad, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<2, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], [9, 5], - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<2, [LWB]>], + [P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], [9, 5], - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStStore, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<2, [LWB]>], + [P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<2, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStICBI, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTFD, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5, 5], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5, 5], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLFD, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<2, [LWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], [9, 5, 5], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLFDU, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [9, 5, 5], - [NoBypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLHA, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLHAU, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLMW, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLWARX, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1]>, - InstrStage<1, [IRACC], 0>, - InstrStage<4, [LWARX_Hold], 0>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1]>, + InstrStage<1, [P440_IRACC], 0>, + InstrStage<4, [P440_LWARX_Hold], 0>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTD, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<2, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTDU, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<2, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<2, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1]>, - InstrStage<1, [IRACC], 0>, - InstrStage<4, [LWARX_Hold], 0>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1]>, + InstrStage<1, [P440_IRACC], 0>, + InstrStage<4, [P440_LWARX_Hold], 0>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1]>, - InstrStage<1, [IRACC], 0>, - InstrStage<4, [LWARX_Hold], 0>, - InstrStage<1, [LRACC]>, - InstrStage<1, [AGEN]>, - InstrStage<1, [CRD]>, - InstrStage<1, [LWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1]>, + InstrStage<1, [P440_IRACC], 0>, + InstrStage<4, [P440_LWARX_Hold], 0>, + InstrStage<1, [P440_LRACC]>, + InstrStage<1, [P440_AGEN]>, + InstrStage<1, [P440_CRD]>, + InstrStage<1, [P440_LWB]>], [8, 5], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSync, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [LRACC]>, - InstrStage<3, [AGEN], 1>, - InstrStage<2, [CRD], 1>, - InstrStage<1, [LWB]>]>, - InstrItinData<IIC_SprISYNC, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [FRACC], 0>, - InstrStage<1, [LRACC], 0>, - InstrStage<1, [IRACC]>, - InstrStage<1, [FEXE1], 0>, - InstrStage<1, [AGEN], 0>, - InstrStage<1, [JEXE1], 0>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [FEXE2], 0>, - InstrStage<1, [CRD], 0>, - InstrStage<1, [JEXE2], 0>, - InstrStage<1, [IEXE2]>, - InstrStage<6, [FEXE3], 0>, - InstrStage<6, [LWB], 0>, - InstrStage<6, [JWB], 0>, - InstrStage<6, [IWB]>]>, - InstrItinData<IIC_SprMFSR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_LRACC]>, + InstrStage<3, [P440_AGEN], 1>, + InstrStage<2, [P440_CRD], 1>, + InstrStage<1, [P440_LWB]>]>, + InstrItinData<IIC_SprISYNC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_FRACC], 0>, + InstrStage<1, [P440_LRACC], 0>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_FEXE1], 0>, + InstrStage<1, [P440_AGEN], 0>, + InstrStage<1, [P440_JEXE1], 0>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_FEXE2], 0>, + InstrStage<1, [P440_CRD], 0>, + InstrStage<1, [P440_JEXE2], 0>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<6, [P440_FEXE3], 0>, + InstrStage<6, [P440_LWB], 0>, + InstrStage<6, [P440_JWB], 0>, + InstrStage<6, [P440_IWB]>]>, + InstrItinData<IIC_SprMFSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [6, 4], - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTMSR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [6, 4], - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTSR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<3, [IWB]>], + [P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<3, [P440_IWB]>], [9, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>]>, - InstrItinData<IIC_SprMFCR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>]>, + InstrItinData<IIC_SprMFCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprMFMSR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [7, 4], - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprMFSPR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<3, [IWB]>], + [P440_GPR_Bypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<3, [P440_IWB]>], [10, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprMFTB, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<3, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<3, [P440_IWB]>], [10, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTSPR, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<3, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<3, [P440_IWB]>], [10, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<3, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<3, [P440_IWB]>], [10, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprRFI, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprSC, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [IRACC]>, - InstrStage<1, [IEXE1]>, - InstrStage<1, [IEXE2]>, - InstrStage<1, [IWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_SprSC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_IRACC]>, + InstrStage<1, [P440_IEXE1]>, + InstrStage<1, [P440_IEXE2]>, + InstrStage<1, [P440_IWB]>], [8, 4], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_FPGeneral, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [FRACC]>, - InstrStage<1, [FEXE1]>, - InstrStage<1, [FEXE2]>, - InstrStage<1, [FEXE3]>, - InstrStage<1, [FEXE4]>, - InstrStage<1, [FEXE5]>, - InstrStage<1, [FEXE6]>, - InstrStage<1, [FWB]>], + [NoBypass, P440_GPR_Bypass]>, + InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_FRACC]>, + InstrStage<1, [P440_FEXE1]>, + InstrStage<1, [P440_FEXE2]>, + InstrStage<1, [P440_FEXE3]>, + InstrStage<1, [P440_FEXE4]>, + InstrStage<1, [P440_FEXE5]>, + InstrStage<1, [P440_FEXE6]>, + InstrStage<1, [P440_FWB]>], [10, 4, 4], - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPAddSub, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [FRACC]>, - InstrStage<1, [FEXE1]>, - InstrStage<1, [FEXE2]>, - InstrStage<1, [FEXE3]>, - InstrStage<1, [FEXE4]>, - InstrStage<1, [FEXE5]>, - InstrStage<1, [FEXE6]>, - InstrStage<1, [FWB]>], + [P440_FPR_Bypass, + P440_FPR_Bypass, P440_FPR_Bypass]>, + InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_FRACC]>, + InstrStage<1, [P440_FEXE1]>, + InstrStage<1, [P440_FEXE2]>, + InstrStage<1, [P440_FEXE3]>, + InstrStage<1, [P440_FEXE4]>, + InstrStage<1, [P440_FEXE5]>, + InstrStage<1, [P440_FEXE6]>, + InstrStage<1, [P440_FWB]>], [10, 4, 4], - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPCompare, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [FRACC]>, - InstrStage<1, [FEXE1]>, - InstrStage<1, [FEXE2]>, - InstrStage<1, [FEXE3]>, - InstrStage<1, [FEXE4]>, - InstrStage<1, [FEXE5]>, - InstrStage<1, [FEXE6]>, - InstrStage<1, [FWB]>], + [P440_FPR_Bypass, + P440_FPR_Bypass, P440_FPR_Bypass]>, + InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_FRACC]>, + InstrStage<1, [P440_FEXE1]>, + InstrStage<1, [P440_FEXE2]>, + InstrStage<1, [P440_FEXE3]>, + InstrStage<1, [P440_FEXE4]>, + InstrStage<1, [P440_FEXE5]>, + InstrStage<1, [P440_FEXE6]>, + InstrStage<1, [P440_FWB]>], [10, 4, 4], - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPDivD, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [FRACC]>, - InstrStage<1, [FEXE1]>, - InstrStage<1, [FEXE2]>, - InstrStage<1, [FEXE3]>, - InstrStage<1, [FEXE4]>, - InstrStage<1, [FEXE5]>, - InstrStage<1, [FEXE6]>, - InstrStage<25, [FWB]>], + [P440_FPR_Bypass, P440_FPR_Bypass, + P440_FPR_Bypass]>, + InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_FRACC]>, + InstrStage<1, [P440_FEXE1]>, + InstrStage<1, [P440_FEXE2]>, + InstrStage<1, [P440_FEXE3]>, + InstrStage<1, [P440_FEXE4]>, + InstrStage<1, [P440_FEXE5]>, + InstrStage<1, [P440_FEXE6]>, + InstrStage<25, [P440_FWB]>], [35, 4, 4], - [NoBypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPDivS, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [FRACC]>, - InstrStage<1, [FEXE1]>, - InstrStage<1, [FEXE2]>, - InstrStage<1, [FEXE3]>, - InstrStage<1, [FEXE4]>, - InstrStage<1, [FEXE5]>, - InstrStage<1, [FEXE6]>, - InstrStage<13, [FWB]>], + [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>, + InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_FRACC]>, + InstrStage<1, [P440_FEXE1]>, + InstrStage<1, [P440_FEXE2]>, + InstrStage<1, [P440_FEXE3]>, + InstrStage<1, [P440_FEXE4]>, + InstrStage<1, [P440_FEXE5]>, + InstrStage<1, [P440_FEXE6]>, + InstrStage<13, [P440_FWB]>], [23, 4, 4], - [NoBypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPFused, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [FRACC]>, - InstrStage<1, [FEXE1]>, - InstrStage<1, [FEXE2]>, - InstrStage<1, [FEXE3]>, - InstrStage<1, [FEXE4]>, - InstrStage<1, [FEXE5]>, - InstrStage<1, [FEXE6]>, - InstrStage<1, [FWB]>], + [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>, + InstrItinData<IIC_FPFused, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_FRACC]>, + InstrStage<1, [P440_FEXE1]>, + InstrStage<1, [P440_FEXE2]>, + InstrStage<1, [P440_FEXE3]>, + InstrStage<1, [P440_FEXE4]>, + InstrStage<1, [P440_FEXE5]>, + InstrStage<1, [P440_FEXE6]>, + InstrStage<1, [P440_FWB]>], [10, 4, 4, 4], - [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPRes, [InstrStage<1, [IFTH1, IFTH2]>, - InstrStage<1, [PDCD1, PDCD2]>, - InstrStage<1, [DISS1, DISS2]>, - InstrStage<1, [FRACC]>, - InstrStage<1, [FEXE1]>, - InstrStage<1, [FEXE2]>, - InstrStage<1, [FEXE3]>, - InstrStage<1, [FEXE4]>, - InstrStage<1, [FEXE5]>, - InstrStage<1, [FEXE6]>, - InstrStage<1, [FWB]>], + [P440_FPR_Bypass, + P440_FPR_Bypass, P440_FPR_Bypass, + P440_FPR_Bypass]>, + InstrItinData<IIC_FPRes, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>, + InstrStage<1, [P440_PDCD1, P440_PDCD2]>, + InstrStage<1, [P440_DISS1, P440_DISS2]>, + InstrStage<1, [P440_FRACC]>, + InstrStage<1, [P440_FEXE1]>, + InstrStage<1, [P440_FEXE2]>, + InstrStage<1, [P440_FEXE3]>, + InstrStage<1, [P440_FEXE4]>, + InstrStage<1, [P440_FEXE5]>, + InstrStage<1, [P440_FEXE6]>, + InstrStage<1, [P440_FWB]>], [10, 4], - [FPR_Bypass, FPR_Bypass]> + [P440_FPR_Bypass, P440_FPR_Bypass]> ]>; diff --git a/lib/Target/PowerPC/PPCScheduleA2.td b/lib/Target/PowerPC/PPCScheduleA2.td index 0dadcd6531..509de816aa 100644 --- a/lib/Target/PowerPC/PPCScheduleA2.td +++ b/lib/Target/PowerPC/PPCScheduleA2.td @@ -14,8 +14,8 @@ //===----------------------------------------------------------------------===// // Functional units on the PowerPC A2 chip sets // -def XU : FuncUnit; // XU pipeline -def FU : FuncUnit; // FI pipeline +def A2_XU : FuncUnit; // A2_XU pipeline +def A2_FU : FuncUnit; // FI pipeline // // This file defines the itinerary class data for the PPC A2 processor. @@ -24,118 +24,118 @@ def FU : FuncUnit; // FI pipeline def PPCA2Itineraries : ProcessorItineraries< - [XU, FU], [], [ - InstrItinData<IIC_IntSimple, [InstrStage<1, [XU]>], + [A2_XU, A2_FU], [], [ + InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_IntGeneral, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>], [2, 1, 1]>, - InstrItinData<IIC_IntCompare, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>], [2, 1, 1]>, - InstrItinData<IIC_IntDivW, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>], [39, 1, 1]>, - InstrItinData<IIC_IntDivD, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>], [71, 1, 1]>, - InstrItinData<IIC_IntMulHW, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>], [5, 1, 1]>, - InstrItinData<IIC_IntMulHWU, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>], [5, 1, 1]>, - InstrItinData<IIC_IntMulLI, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>], [6, 1, 1]>, - InstrItinData<IIC_IntRotate, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>], [2, 1, 1]>, - InstrItinData<IIC_IntRotateD, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntRotateD, [InstrStage<1, [A2_XU]>], [2, 1, 1]>, - InstrItinData<IIC_IntRotateDI, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>], [2, 1, 1]>, - InstrItinData<IIC_IntShift, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntShift, [InstrStage<1, [A2_XU]>], [2, 1, 1]>, - InstrItinData<IIC_IntTrapW, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntTrapW, [InstrStage<1, [A2_XU]>], [2, 1]>, - InstrItinData<IIC_IntTrapD, [InstrStage<1, [XU]>], + InstrItinData<IIC_IntTrapD, [InstrStage<1, [A2_XU]>], [2, 1]>, - InstrItinData<IIC_BrB, [InstrStage<1, [XU]>], + InstrItinData<IIC_BrB, [InstrStage<1, [A2_XU]>], [6, 1, 1]>, - InstrItinData<IIC_BrCR, [InstrStage<1, [XU]>], + InstrItinData<IIC_BrCR, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_BrMCR, [InstrStage<1, [XU]>], + InstrItinData<IIC_BrMCR, [InstrStage<1, [A2_XU]>], [5, 1, 1]>, - InstrItinData<IIC_BrMCRX, [InstrStage<1, [XU]>], + InstrItinData<IIC_BrMCRX, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_LdStDCBA, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStDCBA, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_LdStDCBF, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStDCBF, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_LdStDCBI, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStDCBI, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_LdStLoad, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStLoad, [InstrStage<1, [A2_XU]>], [6, 1, 1]>, - InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>], [6, 8, 1, 1]>, - InstrItinData<IIC_LdStLDU, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>], [6, 1, 1]>, - InstrItinData<IIC_LdStStore, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [XU]>], + InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>], [2, 1, 1, 1]>, - InstrItinData<IIC_LdStICBI, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>], [16, 1, 1]>, - InstrItinData<IIC_LdStSTFD, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>], [2, 1, 1, 1]>, - InstrItinData<IIC_LdStLFD, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStLFD, [InstrStage<1, [A2_XU]>], [7, 1, 1]>, - InstrItinData<IIC_LdStLFDU, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>], [7, 9, 1, 1]>, - InstrItinData<IIC_LdStLHA, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>], [6, 1, 1]>, - InstrItinData<IIC_LdStLHAU, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>], [6, 8, 1, 1]>, - InstrItinData<IIC_LdStLWARX, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>], [82, 1, 1]>, // L2 latency - InstrItinData<IIC_LdStSTD, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>], [1, 1, 1]>, - InstrItinData<IIC_LdStSTDU, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>], [2, 1, 1, 1]>, - InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>], [82, 1, 1]>, // L2 latency - InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>], [82, 1, 1]>, // L2 latency - InstrItinData<IIC_LdStSync, [InstrStage<1, [XU]>], + InstrItinData<IIC_LdStSync, [InstrStage<1, [A2_XU]>], [6]>, - InstrItinData<IIC_SprISYNC, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprISYNC, [InstrStage<1, [A2_XU]>], [16]>, - InstrItinData<IIC_SprMTMSR, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprMTMSR, [InstrStage<1, [A2_XU]>], [16, 1]>, - InstrItinData<IIC_SprMFCR, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>], [6, 1]>, - InstrItinData<IIC_SprMFMSR, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>], [4, 1]>, - InstrItinData<IIC_SprMFSPR, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>], [6, 1]>, - InstrItinData<IIC_SprMFTB, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprMFTB, [InstrStage<1, [A2_XU]>], [4, 1]>, - InstrItinData<IIC_SprMTSPR, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprMTSPR, [InstrStage<1, [A2_XU]>], [6, 1]>, - InstrItinData<IIC_SprRFI, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprRFI, [InstrStage<1, [A2_XU]>], [16]>, - InstrItinData<IIC_SprSC, [InstrStage<1, [XU]>], + InstrItinData<IIC_SprSC, [InstrStage<1, [A2_XU]>], [16]>, - InstrItinData<IIC_FPGeneral, [InstrStage<1, [FU]>], + InstrItinData<IIC_FPGeneral, [InstrStage<1, [A2_FU]>], [6, 1, 1]>, - InstrItinData<IIC_FPAddSub, [InstrStage<1, [FU]>], + InstrItinData<IIC_FPAddSub, [InstrStage<1, [A2_FU]>], [6, 1, 1]>, - InstrItinData<IIC_FPCompare, [InstrStage<1, [FU]>], + InstrItinData<IIC_FPCompare, [InstrStage<1, [A2_FU]>], [5, 1, 1]>, - InstrItinData<IIC_FPDivD, [InstrStage<1, [FU]>], + InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>], [72, 1, 1]>, - InstrItinData<IIC_FPDivS, [InstrStage<1, [FU]>], + InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>], [59, 1, 1]>, - InstrItinData<IIC_FPSqrt, [InstrStage<1, [FU]>], + InstrItinData<IIC_FPSqrt, [InstrStage<1, [A2_FU]>], [69, 1, 1]>, - InstrItinData<IIC_FPFused, [InstrStage<1, [FU]>], + InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>], [6, 1, 1, 1]>, - InstrItinData<IIC_FPRes, [InstrStage<1, [FU]>], + InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>], [6, 1]> ]>; diff --git a/lib/Target/PowerPC/PPCScheduleE500mc.td b/lib/Target/PowerPC/PPCScheduleE500mc.td index 6560a92c26..906c685d54 100644 --- a/lib/Target/PowerPC/PPCScheduleE500mc.td +++ b/lib/Target/PowerPC/PPCScheduleE500mc.td @@ -19,238 +19,263 @@ // * Decode & Dispatch // Can dispatch up to 2 instructions per clock cycle to either the GPR Issue // queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ). -def DIS0 : FuncUnit; // Dispatch stage - insn 1 -def DIS1 : FuncUnit; // Dispatch stage - insn 2 +def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1 +def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2 // * Execute // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX. // Some instructions can only execute in SFX0 but not SFX1. // The CFX has a bypass path, allowing non-divide instructions to execute // while a divide instruction is executed. -def SFX0 : FuncUnit; // Simple unit 0 -def SFX1 : FuncUnit; // Simple unit 1 -def BU : FuncUnit; // Branch unit -def CFX_DivBypass - : FuncUnit; // CFX divide bypass path -def CFX_0 : FuncUnit; // CFX pipeline -def LSU_0 : FuncUnit; // LSU pipeline -def FPU_0 : FuncUnit; // FPU pipeline +def E500_SFX0 : FuncUnit; // Simple unit 0 +def E500_SFX1 : FuncUnit; // Simple unit 1 +def E500_BU : FuncUnit; // Branch unit +def E500_CFX_DivBypass + : FuncUnit; // CFX divide bypass path +def E500_CFX_0 : FuncUnit; // CFX pipeline +def E500_LSU_0 : FuncUnit; // LSU pipeline +def E500_FPU_0 : FuncUnit; // FPU pipeline -def CR_Bypass : Bypass; +def E500_GPR_Bypass : Bypass; +def E500_FPR_Bypass : Bypass; +def E500_CR_Bypass : Bypass; def PPCE500mcItineraries : ProcessorItineraries< - [DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, LSU_0, FPU_0], - [CR_Bypass, GPR_Bypass, FPR_Bypass], [ - InstrItinData<IIC_IntSimple, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass, + E500_CFX_0, E500_LSU_0, E500_FPU_0], + [E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [ + InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1, 1], // Latency = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntGeneral, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1, 1], // Latency = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntCompare, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1]>], [5, 1, 1], // Latency = 1 or 2 - [CR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntDivW, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0], 0>, - InstrStage<14, [CFX_DivBypass]>], + [E500_CR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_CFX_0], 0>, + InstrStage<14, [E500_CFX_DivBypass]>], [17, 1, 1], // Latency=4..35, Repeat= 4..35 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMFFS, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<8, [FPU_0]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<8, [E500_FPU_0]>], [11], // Latency = 8 - [FPR_Bypass]>, - InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<8, [FPU_0]>], + [E500_FPR_Bypass]>, + InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<8, [E500_FPU_0]>], [11, 1, 1], // Latency = 8 [NoBypass, NoBypass, NoBypass]>, - InstrItinData<IIC_IntMulHW, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0]>], + InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_CFX_0]>], [7, 1, 1], // Latency = 4, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMulHWU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_CFX_0]>], [7, 1, 1], // Latency = 4, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMulLI, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_CFX_0]>], [7, 1, 1], // Latency = 4, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntRotate, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1, 1], // Latency = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntShift, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1, 1], // Latency = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntTrapW, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [SFX0]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<2, [E500_SFX0]>], [5, 1], // Latency = 2, Repeat rate = 2 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_BrB, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [BU]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_BU]>], [4, 1], // Latency = 1 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_BrCR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [BU]>], + [NoBypass, E500_GPR_Bypass]>, + InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_BU]>], [4, 1, 1], // Latency = 1 - [CR_Bypass, CR_Bypass, CR_Bypass]>, - InstrItinData<IIC_BrMCR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [BU]>], + [E500_CR_Bypass, + E500_CR_Bypass, E500_CR_Bypass]>, + InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_BU]>], [4, 1], // Latency = 1 - [CR_Bypass, CR_Bypass]>, - InstrItinData<IIC_BrMCRX, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E500_CR_Bypass, E500_CR_Bypass]>, + InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1, 1], // Latency = 1 - [CR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBA, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E500_CR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBF, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBI, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLoad, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [GPR_Bypass, GPR_Bypass], - 2>, // 2 micro-ops - InstrItinData<IIC_LdStStore, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, E500_GPR_Bypass], + 2>, // 2 micro-ops + InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [NoBypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [NoBypass, GPR_Bypass], - 2>, // 2 micro-ops - InstrItinData<IIC_LdStICBI, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [NoBypass, E500_GPR_Bypass], + 2>, // 2 micro-ops + InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTFD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [NoBypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1, 1], // Latency = 3 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1, 1], // Latency = 3 - [GPR_Bypass, GPR_Bypass, GPR_Bypass], - 2>, // 2 micro-ops - InstrItinData<IIC_LdStLFD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass], + 2>, // 2 micro-ops + InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [7, 1, 1], // Latency = 4 - [FPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLFDU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E500_FPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1], 0>, + InstrStage<1, [E500_LSU_0]>], [7, 1, 1], // Latency = 4 - [FPR_Bypass, GPR_Bypass, GPR_Bypass], + [E500_FPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass], 2>, // 2 micro-ops - InstrItinData<IIC_LdStLHA, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLHAU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLMW, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [7, 1], // Latency = r+3 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLWARX, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<3, [LSU_0]>], + [NoBypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<3, [E500_LSU_0]>], [6, 1, 1], // Latency = 3, Repeat rate = 3 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E500_GPR_Bypass, + E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>], [6, 1], // Latency = 3 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSync, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>]>, - InstrItinData<IIC_SprMFSR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<4, [SFX0]>], + [NoBypass, E500_GPR_Bypass]>, + InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0]>]>, + InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<4, [E500_SFX0]>], [7, 1], - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTMSR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [SFX0, SFX1]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<2, [E500_SFX0, E500_SFX1]>], [5, 1], // Latency = 2, Repeat rate = 4 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTSR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0]>], [5, 1], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0], 0>]>, - InstrItinData<IIC_SprMFCR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<5, [SFX0]>], + [NoBypass, E500_GPR_Bypass]>, + InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_LSU_0], 0>]>, + InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<5, [E500_SFX0]>], [8, 1], - [GPR_Bypass, CR_Bypass]>, - InstrItinData<IIC_SprMFMSR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<4, [SFX0]>], + [E500_GPR_Bypass, E500_CR_Bypass]>, + InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<4, [E500_SFX0]>], [7, 1], // Latency = 4, Repeat rate = 4 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprMFSPR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E500_GPR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1], // Latency = 1, Repeat rate = 1 - [GPR_Bypass, CR_Bypass]>, - InstrItinData<IIC_SprMFTB, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<4, [SFX0]>], + [E500_GPR_Bypass, E500_CR_Bypass]>, + InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<4, [E500_SFX0]>], [7, 1], // Latency = 4, Repeat rate = 4 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTSPR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [NoBypass, E500_GPR_Bypass]>, + InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0, E500_SFX1]>], [4, 1], // Latency = 1, Repeat rate = 1 - [CR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0]>], + [E500_CR_Bypass, E500_GPR_Bypass]>, + InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<1, [E500_SFX0]>], [4, 1], - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_FPGeneral, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [FPU_0]>], + [NoBypass, E500_GPR_Bypass]>, + InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<2, [E500_FPU_0]>], [11, 1, 1], // Latency = 8, Repeat rate = 2 - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPAddSub, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<4, [FPU_0]>], + [E500_FPR_Bypass, + E500_FPR_Bypass, E500_FPR_Bypass]>, + InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<4, [E500_FPU_0]>], [13, 1, 1], // Latency = 10, Repeat rate = 4 - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPCompare, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [FPU_0]>], + [E500_FPR_Bypass, + E500_FPR_Bypass, E500_FPR_Bypass]>, + InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<2, [E500_FPU_0]>], [11, 1, 1], // Latency = 8, Repeat rate = 2 - [CR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPDivD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<68, [FPU_0]>], + [E500_CR_Bypass, + E500_FPR_Bypass, E500_FPR_Bypass]>, + InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<68, [E500_FPU_0]>], [71, 1, 1], // Latency = 68, Repeat rate = 68 - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPDivS, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<38, [FPU_0]>], + [E500_FPR_Bypass, + E500_FPR_Bypass, E500_FPR_Bypass]>, + InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<38, [E500_FPU_0]>], [41, 1, 1], // Latency = 38, Repeat rate = 38 - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPFused, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<4, [FPU_0]>], + [E500_FPR_Bypass, + E500_FPR_Bypass, E500_FPR_Bypass]>, + InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<4, [E500_FPU_0]>], [13, 1, 1, 1], // Latency = 10, Repeat rate = 4 - [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPRes, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<38, [FPU_0]>], + [E500_FPR_Bypass, + E500_FPR_Bypass, E500_FPR_Bypass, + E500_FPR_Bypass]>, + InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, + InstrStage<38, [E500_FPU_0]>], [41, 1], // Latency = 38, Repeat rate = 38 - [FPR_Bypass, FPR_Bypass]> + [E500_FPR_Bypass, E500_FPR_Bypass]> ]>; // ===---------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCScheduleE5500.td b/lib/Target/PowerPC/PPCScheduleE5500.td index f431ac3f70..0de04fb2be 100644 --- a/lib/Target/PowerPC/PPCScheduleE5500.td +++ b/lib/Target/PowerPC/PPCScheduleE5500.td @@ -20,280 +20,309 @@ // * Decode & Dispatch // Can dispatch up to 2 instructions per clock cycle to either the GPR Issue // queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ). -// def DIS0 : FuncUnit; -// def DIS1 : FuncUnit; +def E5500_DIS0 : FuncUnit; +def E5500_DIS1 : FuncUnit; // * Execute // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX. // The CFX has a bypass path, allowing non-divide instructions to execute // while a divide instruction is being executed. -// def SFX0 : FuncUnit; // Simple unit 0 -// def SFX1 : FuncUnit; // Simple unit 1 -// def BU : FuncUnit; // Branch unit -// def CFX_DivBypass -// : FuncUnit; // CFX divide bypass path -// def CFX_0 : FuncUnit; // CFX pipeline stage 0 +def E5500_SFX0 : FuncUnit; // Simple unit 0 +def E5500_SFX1 : FuncUnit; // Simple unit 1 +def E5500_BU : FuncUnit; // Branch unit +def E5500_CFX_DivBypass + : FuncUnit; // CFX divide bypass path +def E5500_CFX_0 : FuncUnit; // CFX pipeline stage 0 -def CFX_1 : FuncUnit; // CFX pipeline stage 1 +def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1 -// def LSU_0 : FuncUnit; // LSU pipeline -// def FPU_0 : FuncUnit; // FPU pipeline +def E5500_LSU_0 : FuncUnit; // LSU pipeline +def E5500_FPU_0 : FuncUnit; // FPU pipeline -// def CR_Bypass : Bypass; +def E5500_GPR_Bypass : Bypass; +def E5500_FPR_Bypass : Bypass; +def E5500_CR_Bypass : Bypass; def PPCE5500Itineraries : ProcessorItineraries< - [DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, CFX_1, - LSU_0, FPU_0], - [CR_Bypass, GPR_Bypass, FPR_Bypass], [ - InstrItinData<IIC_IntSimple, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E5500_DIS0, E5500_DIS1, E5500_SFX0, E5500_SFX1, E5500_BU, + E5500_CFX_DivBypass, E5500_CFX_0, E5500_CFX_1, + E5500_LSU_0, E5500_FPU_0], + [E5500_CR_Bypass, E5500_GPR_Bypass, E5500_FPR_Bypass], [ + InstrItinData<IIC_IntSimple, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1]>], [5, 2, 2], // Latency = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntGeneral, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1]>], [5, 2, 2], // Latency = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntCompare, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1]>], [6, 2, 2], // Latency = 1 or 2 - [CR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntDivD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0], 0>, - InstrStage<26, [CFX_DivBypass]>], + [E5500_CR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0], 0>, + InstrStage<26, [E5500_CFX_DivBypass]>], [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntDivW, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0], 0>, - InstrStage<16, [CFX_DivBypass]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntDivW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0], 0>, + InstrStage<16, [E5500_CFX_DivBypass]>], [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMFFS, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [FPU_0]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntMFFS, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_FPU_0]>], [11], // Latency = 7, Repeat rate = 1 - [FPR_Bypass]>, - InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<7, [FPU_0]>], + [E5500_FPR_Bypass]>, + InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<7, [E5500_FPU_0]>], [11, 2, 2], // Latency = 7, Repeat rate = 7 [NoBypass, NoBypass, NoBypass]>, - InstrItinData<IIC_IntMulHD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0], 0>, - InstrStage<2, [CFX_1]>], + InstrItinData<IIC_IntMulHD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0], 0>, + InstrStage<2, [E5500_CFX_1]>], [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMulHW, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0], 0>, - InstrStage<1, [CFX_1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntMulHW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0], 0>, + InstrStage<1, [E5500_CFX_1]>], [8, 2, 2], // Latency = 4, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMulHWU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0], 0>, - InstrStage<1, [CFX_1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0], 0>, + InstrStage<1, [E5500_CFX_1]>], [8, 2, 2], // Latency = 4, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntMulLI, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0], 0>, - InstrStage<2, [CFX_1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntMulLI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0], 0>, + InstrStage<2, [E5500_CFX_1]>], [8, 2, 2], // Latency = 4 or 5, Repeat = 2 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntRotate, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntRotate, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1]>], [5, 2, 2], // Latency = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntRotateD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [SFX0, SFX1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntRotateD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<2, [E5500_SFX0, E5500_SFX1]>], [6, 2, 2], // Latency = 2, Repeat rate = 2 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntRotateDI, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntRotateDI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1]>], [5, 2, 2], // Latency = 1, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntShift, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [SFX0, SFX1]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntShift, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<2, [E5500_SFX0, E5500_SFX1]>], [6, 2, 2], // Latency = 2, Repeat rate = 2 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_IntTrapW, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [SFX0]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_IntTrapW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<2, [E5500_SFX0]>], [6, 2], // Latency = 2, Repeat rate = 2 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_BrB, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [BU]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_BrB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_BU]>], [5, 2], // Latency = 1 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_BrCR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [BU]>], + [NoBypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_BrCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_BU]>], [5, 2, 2], // Latency = 1 - [CR_Bypass, CR_Bypass, CR_Bypass]>, - InstrItinData<IIC_BrMCR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [BU]>], + [E5500_CR_Bypass, + E5500_CR_Bypass, E5500_CR_Bypass]>, + InstrItinData<IIC_BrMCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_BU]>], [5, 2], // Latency = 1 - [CR_Bypass, CR_Bypass]>, - InstrItinData<IIC_BrMCRX, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0]>], + [E5500_CR_Bypass, E5500_CR_Bypass]>, + InstrItinData<IIC_BrMCRX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0]>], [5, 2, 2], // Latency = 1 - [CR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBA, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_CR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBF, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStDCBI, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLoad, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStLoad, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass], + [E5500_GPR_Bypass, E5500_GPR_Bypass], 2>, // 2 micro-ops - InstrItinData<IIC_LdStLD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + InstrItinData<IIC_LdStLD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLDARX, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<3, [LSU_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStLDARX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<3, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 3 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLDU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStLDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass], + [E5500_GPR_Bypass, E5500_GPR_Bypass], 2>, // 2 micro-ops - InstrItinData<IIC_LdStStore, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + InstrItinData<IIC_LdStStore, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [NoBypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [NoBypass, GPR_Bypass], - 2>, // 2 micro-ops - InstrItinData<IIC_LdStICBI, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [NoBypass, E5500_GPR_Bypass], + 2>, // 2 micro-ops + InstrItinData<IIC_LdStICBI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTFD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [NoBypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass, GPR_Bypass], - 2>, // 2 micro-ops - InstrItinData<IIC_LdStLFD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass], + 2>, // 2 micro-ops + InstrItinData<IIC_LdStLFD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [8, 2, 2], // Latency = 4, Repeat rate = 1 - [FPR_Bypass, GPR_Bypass, GPR_Bypass], + [E5500_FPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass], 2>, // 2 micro-ops - InstrItinData<IIC_LdStLFDU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>, + InstrStage<1, [E5500_LSU_0]>], [8, 2, 2], // Latency = 4, Repeat rate = 1 - [FPR_Bypass, GPR_Bypass, GPR_Bypass], + [E5500_FPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass], 2>, // 2 micro-ops - InstrItinData<IIC_LdStLHA, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + InstrItinData<IIC_LdStLHA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLHAU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [GPR_Bypass, GPR_Bypass], - 2>, // 2 micro-ops - InstrItinData<IIC_LdStLMW, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<4, [LSU_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass], + 2>, // 2 micro-ops + InstrItinData<IIC_LdStLMW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<4, [E5500_LSU_0]>], [8, 2], // Latency = r+3, Repeat rate = r+3 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStLWARX, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<3, [LSU_0]>], + [NoBypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<3, [E5500_LSU_0]>], [7, 2, 2], // Latency = 3, Repeat rate = 3 - [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], - [7, 2], // Latency = 3, Repeat rate = 1 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], - [7, 2], // Latency = 3, Repeat rate = 1 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSTDU, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1], 0>, - InstrStage<1, [LSU_0]>], + [E5500_GPR_Bypass, + E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStSTD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [NoBypass, GPR_Bypass], - 2>, // 2 micro-ops - InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>], + [NoBypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], + [7, 2], // Latency = 3, Repeat rate = 1 + [NoBypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStSTDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>, + InstrStage<1, [E5500_LSU_0]>], + [7, 2], // Latency = 3, Repeat rate = 1 + [NoBypass, E5500_GPR_Bypass], + 2>, // 2 micro-ops + InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>], [7, 2], // Latency = 3, Repeat rate = 1 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_LdStSync, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0]>]>, - InstrItinData<IIC_SprMTMSR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [CFX_0]>], + [NoBypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_LdStSync, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0]>]>, + InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<2, [E5500_CFX_0]>], [6, 2], // Latency = 2, Repeat rate = 4 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [LSU_0], 0>]>, - InstrItinData<IIC_SprMFCR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<5, [CFX_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_LSU_0], 0>]>, + InstrItinData<IIC_SprMFCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<5, [E5500_CFX_0]>], [9, 2], // Latency = 5, Repeat rate = 5 - [GPR_Bypass, CR_Bypass]>, - InstrItinData<IIC_SprMFMSR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<4, [SFX0]>], + [E5500_GPR_Bypass, E5500_CR_Bypass]>, + InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<4, [E5500_SFX0]>], [8, 2], // Latency = 4, Repeat rate = 4 - [GPR_Bypass, GPR_Bypass]>, - InstrItinData<IIC_SprMFSPR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [CFX_0]>], + [E5500_GPR_Bypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_CFX_0]>], [5], // Latency = 1, Repeat rate = 1 - [GPR_Bypass]>, - InstrItinData<IIC_SprMFTB, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<4, [CFX_0]>], + [E5500_GPR_Bypass]>, + InstrItinData<IIC_SprMFTB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<4, [E5500_CFX_0]>], [8, 2], // Latency = 4, Repeat rate = 4 - [NoBypass, GPR_Bypass]>, - InstrItinData<IIC_SprMTSPR, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [SFX0, SFX1]>], + [NoBypass, E5500_GPR_Bypass]>, + InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_SFX0, E5500_SFX1]>], [5], // Latency = 1, Repeat rate = 1 - [GPR_Bypass]>, - InstrItinData<IIC_FPGeneral, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [FPU_0]>], + [E5500_GPR_Bypass]>, + InstrItinData<IIC_FPGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_FPU_0]>], [11, 2, 2], // Latency = 7, Repeat rate = 1 - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPAddSub, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [FPU_0]>], + [E5500_FPR_Bypass, + E5500_FPR_Bypass, E5500_FPR_Bypass]>, + InstrItinData<IIC_FPAddSub, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_FPU_0]>], [11, 2, 2], // Latency = 7, Repeat rate = 1 - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPCompare, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [FPU_0]>], + [E5500_FPR_Bypass, + E5500_FPR_Bypass, E5500_FPR_Bypass]>, + InstrItinData<IIC_FPCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_FPU_0]>], [11, 2, 2], // Latency = 7, Repeat rate = 1 - [CR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPDivD, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<31, [FPU_0]>], + [E5500_CR_Bypass, + E5500_FPR_Bypass, E5500_FPR_Bypass]>, + InstrItinData<IIC_FPDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<31, [E5500_FPU_0]>], [39, 2, 2], // Latency = 35, Repeat rate = 31 - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPDivS, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<16, [FPU_0]>], + [E5500_FPR_Bypass, + E5500_FPR_Bypass, E5500_FPR_Bypass]>, + InstrItinData<IIC_FPDivS, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<16, [E5500_FPU_0]>], [24, 2, 2], // Latency = 20, Repeat rate = 16 - [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPFused, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<1, [FPU_0]>], + [E5500_FPR_Bypass, + E5500_FPR_Bypass, E5500_FPR_Bypass]>, + InstrItinData<IIC_FPFused, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<1, [E5500_FPU_0]>], [11, 2, 2, 2], // Latency = 7, Repeat rate = 1 - [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, - InstrItinData<IIC_FPRes, [InstrStage<1, [DIS0, DIS1], 0>, - InstrStage<2, [FPU_0]>], + [E5500_FPR_Bypass, + E5500_FPR_Bypass, E5500_FPR_Bypass, + E5500_FPR_Bypass]>, + InstrItinData<IIC_FPRes, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, + InstrStage<2, [E5500_FPU_0]>], [12, 2], // Latency = 8, Repeat rate = 2 - [FPR_Bypass, FPR_Bypass]> + [E5500_FPR_Bypass, E5500_FPR_Bypass]> ]>; // ===---------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCScheduleG3.td b/lib/Target/PowerPC/PPCScheduleG3.td index df76a843eb..c619297f22 100644 --- a/lib/Target/PowerPC/PPCScheduleG3.td +++ b/lib/Target/PowerPC/PPCScheduleG3.td @@ -11,61 +11,67 @@ // //===----------------------------------------------------------------------===// +def G3_BPU : FuncUnit; // Branch unit +def G3_SLU : FuncUnit; // Store/load unit +def G3_SRU : FuncUnit; // special register unit +def G3_IU1 : FuncUnit; // integer unit 1 (simple) +def G3_IU2 : FuncUnit; // integer unit 2 (complex) +def G3_FPU1 : FuncUnit; // floating point unit 1 def G3Itineraries : ProcessorItineraries< - [IU1, IU2, FPU1, BPU, SRU, SLU], [], [ - InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntDivW , [InstrStage<19, [IU1]>]>, - InstrItinData<IIC_IntMFFS , [InstrStage<1, [FPU1]>]>, - InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [FPU1]>]>, - InstrItinData<IIC_IntMulHW , [InstrStage<5, [IU1]>]>, - InstrItinData<IIC_IntMulHWU , [InstrStage<6, [IU1]>]>, - InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU1]>]>, - InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntShift , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2]>]>, - InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>, - InstrItinData<IIC_BrCR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_BrMCR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_BrMCRX , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_LdStDCBA , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStDCBI , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLoad , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStStore , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStICBI , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTFD , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLFD , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLFDU , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLHA , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLHAU , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLMW , [InstrStage<34, [SLU]>]>, - InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTWCX , [InstrStage<8, [SLU]>]>, - InstrItinData<IIC_LdStSync , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_SprISYNC , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprMFSR , [InstrStage<3, [SRU]>]>, - InstrItinData<IIC_SprMTMSR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_SprMTSR , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SRU]>]>, - InstrItinData<IIC_SprMFCR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_SprMFMSR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_SprMFSPR , [InstrStage<3, [SRU]>]>, - InstrItinData<IIC_SprMFTB , [InstrStage<3, [SRU]>]>, - InstrItinData<IIC_SprMTSPR , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprRFI , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprSC , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_FPGeneral , [InstrStage<1, [FPU1]>]>, - InstrItinData<IIC_FPAddSub , [InstrStage<1, [FPU1]>]>, - InstrItinData<IIC_FPCompare , [InstrStage<1, [FPU1]>]>, - InstrItinData<IIC_FPDivD , [InstrStage<31, [FPU1]>]>, - InstrItinData<IIC_FPDivS , [InstrStage<17, [FPU1]>]>, - InstrItinData<IIC_FPFused , [InstrStage<2, [FPU1]>]>, - InstrItinData<IIC_FPRes , [InstrStage<10, [FPU1]>]> + [G3_IU1, G3_IU2, G3_FPU1, G3_BPU, G3_SRU, G3_SLU], [], [ + InstrItinData<IIC_IntSimple , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntGeneral , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntCompare , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntDivW , [InstrStage<19, [G3_IU1]>]>, + InstrItinData<IIC_IntMFFS , [InstrStage<1, [G3_FPU1]>]>, + InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G3_FPU1]>]>, + InstrItinData<IIC_IntMulHW , [InstrStage<5, [G3_IU1]>]>, + InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G3_IU1]>]>, + InstrItinData<IIC_IntMulLI , [InstrStage<3, [G3_IU1]>]>, + InstrItinData<IIC_IntRotate , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntShift , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntTrapW , [InstrStage<2, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_BrB , [InstrStage<1, [G3_BPU]>]>, + InstrItinData<IIC_BrCR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_BrMCR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_BrMCRX , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_LdStDCBA , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_LdStLoad , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStStore , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStICBI , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLFD , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLHA , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLMW , [InstrStage<34, [G3_SLU]>]>, + InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_LdStSTWCX , [InstrStage<8, [G3_SLU]>]>, + InstrItinData<IIC_LdStSync , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_SprISYNC , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprMFSR , [InstrStage<3, [G3_SRU]>]>, + InstrItinData<IIC_SprMTMSR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_SprMTSR , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G3_SRU]>]>, + InstrItinData<IIC_SprMFCR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_SprMFMSR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G3_SRU]>]>, + InstrItinData<IIC_SprMFTB , [InstrStage<3, [G3_SRU]>]>, + InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprRFI , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprSC , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_FPGeneral , [InstrStage<1, [G3_FPU1]>]>, + InstrItinData<IIC_FPAddSub , [InstrStage<1, [G3_FPU1]>]>, + InstrItinData<IIC_FPCompare , [InstrStage<1, [G3_FPU1]>]>, + InstrItinData<IIC_FPDivD , [InstrStage<31, [G3_FPU1]>]>, + InstrItinData<IIC_FPDivS , [InstrStage<17, [G3_FPU1]>]>, + InstrItinData<IIC_FPFused , [InstrStage<2, [G3_FPU1]>]>, + InstrItinData<IIC_FPRes , [InstrStage<10, [G3_FPU1]>]> ]>; diff --git a/lib/Target/PowerPC/PPCScheduleG4.td b/lib/Target/PowerPC/PPCScheduleG4.td index 19c0ce3cc0..2b282bfa53 100644 --- a/lib/Target/PowerPC/PPCScheduleG4.td +++ b/lib/Target/PowerPC/PPCScheduleG4.td @@ -11,71 +11,83 @@ // //===----------------------------------------------------------------------===// +def G4_BPU : FuncUnit; // Branch unit +def G4_SLU : FuncUnit; // Store/load unit +def G4_SRU : FuncUnit; // special register unit +def G4_IU1 : FuncUnit; // integer unit 1 (simple) +def G4_IU2 : FuncUnit; // integer unit 2 (complex) +def G4_FPU1 : FuncUnit; // floating point unit 1 +def G4_VPU : FuncUnit; // vector permutation unit +def G4_VIU1 : FuncUnit; // vector integer unit 1 (simple) +def G4_VIU2 : FuncUnit; // vector integer unit 2 (complex) +def G4_VFPU : FuncUnit; // vector floating point unit + def G4Itineraries : ProcessorItineraries< - [IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [], [ - InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntDivW , [InstrStage<19, [IU1]>]>, - InstrItinData<IIC_IntMFFS , [InstrStage<3, [FPU1]>]>, - InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [VIU1]>]>, - InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [FPU1]>]>, - InstrItinData<IIC_IntMulHW , [InstrStage<5, [IU1]>]>, - InstrItinData<IIC_IntMulHWU , [InstrStage<6, [IU1]>]>, - InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU1]>]>, - InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntShift , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2]>]>, - InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>, - InstrItinData<IIC_BrCR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_BrMCR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_BrMCRX , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_LdStDCBF , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStDCBI , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLoad , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStStore , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStDSS , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStICBI , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStSTFD , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLFD , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLFDU , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLHA , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLHAU , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLMW , [InstrStage<34, [SLU]>]>, - InstrItinData<IIC_LdStLVecX , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTVEBX , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStSTWCX , [InstrStage<5, [SLU]>]>, - InstrItinData<IIC_LdStSync , [InstrStage<8, [SLU]>]>, - InstrItinData<IIC_SprISYNC , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprMFSR , [InstrStage<3, [SRU]>]>, - InstrItinData<IIC_SprMTMSR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_SprMTSR , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprTLBSYNC , [InstrStage<8, [SRU]>]>, - InstrItinData<IIC_SprMFCR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_SprMFMSR , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_SprMFSPR , [InstrStage<3, [SRU]>]>, - InstrItinData<IIC_SprMFTB , [InstrStage<1, [SRU]>]>, - InstrItinData<IIC_SprMTSPR , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprRFI , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_SprSC , [InstrStage<2, [SRU]>]>, - InstrItinData<IIC_FPGeneral , [InstrStage<1, [FPU1]>]>, - InstrItinData<IIC_FPAddSub , [InstrStage<1, [FPU1]>]>, - InstrItinData<IIC_FPCompare , [InstrStage<1, [FPU1]>]>, - InstrItinData<IIC_FPDivD , [InstrStage<31, [FPU1]>]>, - InstrItinData<IIC_FPDivS , [InstrStage<17, [FPU1]>]>, - InstrItinData<IIC_FPFused , [InstrStage<1, [FPU1]>]>, - InstrItinData<IIC_FPRes , [InstrStage<10, [FPU1]>]>, - InstrItinData<IIC_VecGeneral , [InstrStage<1, [VIU1]>]>, - InstrItinData<IIC_VecFP , [InstrStage<4, [VFPU]>]>, - InstrItinData<IIC_VecFPCompare, [InstrStage<1, [VIU1]>]>, - InstrItinData<IIC_VecComplex , [InstrStage<3, [VIU2]>]>, - InstrItinData<IIC_VecPerm , [InstrStage<1, [VPU]>]>, - InstrItinData<IIC_VecFPRound , [InstrStage<4, [VFPU]>]>, - InstrItinData<IIC_VecVSL , [InstrStage<1, [VIU1]>]>, - InstrItinData<IIC_VecVSR , [InstrStage<1, [VIU1]>]> + [G4_IU1, G4_IU2, G4_SLU, G4_SRU, G4_BPU, G4_FPU1, + G4_VIU1, G4_VIU2, G4_VPU, G4_VFPU], [], [ + InstrItinData<IIC_IntSimple , [InstrStage<1, [G4_IU1, G4_IU2]>]>, + InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4_IU1, G4_IU2]>]>, + InstrItinData<IIC_IntCompare , [InstrStage<1, [G4_IU1, G4_IU2]>]>, + InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>, + InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>, + InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>, + InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>, + InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>, + InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>, + InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>, + InstrItinData<IIC_IntRotate , [InstrStage<1, [G4_IU1, G4_IU2]>]>, + InstrItinData<IIC_IntShift , [InstrStage<1, [G4_IU1, G4_IU2]>]>, + InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4_IU1, G4_IU2]>]>, + InstrItinData<IIC_BrB , [InstrStage<1, [G4_BPU]>]>, + InstrItinData<IIC_BrCR , [InstrStage<1, [G4_SRU]>]>, + InstrItinData<IIC_BrMCR , [InstrStage<1, [G4_SRU]>]>, + InstrItinData<IIC_BrMCRX , [InstrStage<1, [G4_SRU]>]>, + InstrItinData<IIC_LdStDCBF , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStDCBI , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStLoad , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStStore , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStDSS , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStICBI , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStLFD , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStLHA , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStLMW , [InstrStage<34, [G4_SLU]>]>, + InstrItinData<IIC_LdStLVecX , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4_SLU]>]>, + InstrItinData<IIC_LdStSTVEBX , [InstrStage<2, [G4_SLU]>]>, + InstrItinData<IIC_LdStSTWCX , [InstrStage<5, [G4_SLU]>]>, + InstrItinData<IIC_LdStSync , [InstrStage<8, [G4_SLU]>]>, + InstrItinData<IIC_SprISYNC , [InstrStage<2, [G4_SRU]>]>, + InstrItinData<IIC_SprMFSR , [InstrStage<3, [G4_SRU]>]>, + InstrItinData<IIC_SprMTMSR , [InstrStage<1, [G4_SRU]>]>, + InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4_SRU]>]>, + InstrItinData<IIC_SprTLBSYNC , [InstrStage<8, [G4_SRU]>]>, + InstrItinData<IIC_SprMFCR , [InstrStage<1, [G4_SRU]>]>, + InstrItinData<IIC_SprMFMSR , [InstrStage<1, [G4_SRU]>]>, + InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G4_SRU]>]>, + InstrItinData<IIC_SprMFTB , [InstrStage<1, [G4_SRU]>]>, + InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4_SRU]>]>, + InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4_SRU]>]>, + InstrItinData<IIC_SprRFI , [InstrStage<2, [G4_SRU]>]>, + InstrItinData<IIC_SprSC , [InstrStage<2, [G4_SRU]>]>, + InstrItinData<IIC_FPGeneral , [InstrStage<1, [G4_FPU1]>]>, + InstrItinData<IIC_FPAddSub , [InstrStage<1, [G4_FPU1]>]>, + InstrItinData<IIC_FPCompare , [InstrStage<1, [G4_FPU1]>]>, + InstrItinData<IIC_FPDivD , [InstrStage<31, [G4_FPU1]>]>, + InstrItinData<IIC_FPDivS , [InstrStage<17, [G4_FPU1]>]>, + InstrItinData<IIC_FPFused , [InstrStage<1, [G4_FPU1]>]>, + InstrItinData<IIC_FPRes , [InstrStage<10, [G4_FPU1]>]>, + InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4_VIU1]>]>, + InstrItinData<IIC_VecFP , [InstrStage<4, [G4_VFPU]>]>, + InstrItinData<IIC_VecFPCompare, [InstrStage<1, [G4_VIU1]>]>, + InstrItinData<IIC_VecComplex , [InstrStage<3, [G4_VIU2]>]>, + InstrItinData<IIC_VecPerm , [InstrStage<1, [G4_VPU]>]>, + InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4_VFPU]>]>, + InstrItinData<IIC_VecVSL , [InstrStage<1, [G4_VIU1]>]>, + InstrItinData<IIC_VecVSR , [InstrStage<1, [G4_VIU1]>]> ]>; diff --git a/lib/Target/PowerPC/PPCScheduleG4Plus.td b/lib/Target/PowerPC/PPCScheduleG4Plus.td index 621c926f85..9aaca5dc25 100644 --- a/lib/Target/PowerPC/PPCScheduleG4Plus.td +++ b/lib/Target/PowerPC/PPCScheduleG4Plus.td @@ -11,78 +11,98 @@ // //===----------------------------------------------------------------------===// -def IU3 : FuncUnit; // integer unit 3 (7450 simple) -def IU4 : FuncUnit; // integer unit 4 (7450 simple) +def G4P_BPU : FuncUnit; // Branch unit +def G4P_SLU : FuncUnit; // Store/load unit +def G4P_SRU : FuncUnit; // special register unit +def G4P_IU1 : FuncUnit; // integer unit 1 (simple) +def G4P_IU2 : FuncUnit; // integer unit 2 (complex) +def G4P_IU3 : FuncUnit; // integer unit 3 (simple) +def G4P_IU4 : FuncUnit; // integer unit 4 (simple) +def G4P_FPU1 : FuncUnit; // floating point unit 1 +def G4P_VPU : FuncUnit; // vector permutation unit +def G4P_VIU1 : FuncUnit; // vector integer unit 1 (simple) +def G4P_VIU2 : FuncUnit; // vector integer unit 2 (complex) +def G4P_VFPU : FuncUnit; // vector floating point unit def G4PlusItineraries : ProcessorItineraries< - [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [ - InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_IntDivW , [InstrStage<23, [IU2]>]>, - InstrItinData<IIC_IntMFFS , [InstrStage<5, [FPU1]>]>, - InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [VFPU]>]>, - InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [FPU1]>]>, - InstrItinData<IIC_IntMulHW , [InstrStage<4, [IU2]>]>, - InstrItinData<IIC_IntMulHWU , [InstrStage<4, [IU2]>]>, - InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU2]>]>, - InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>, - InstrItinData<IIC_BrCR , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_BrMCR , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_BrMCRX , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStDCBI , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLoad , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStStore , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStDSS , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStICBI , [InstrStage<3, [IU2]>]>, - InstrItinData<IIC_LdStSTFD , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLFD , [InstrStage<4, [SLU]>]>, - InstrItinData<IIC_LdStLFDU , [InstrStage<4, [SLU]>]>, - InstrItinData<IIC_LdStLHA , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLHAU , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLMW , [InstrStage<37, [SLU]>]>, - InstrItinData<IIC_LdStLVecX , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLWA , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTD , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTDU , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSync , [InstrStage<35, [SLU]>]>, - InstrItinData<IIC_SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_SprMFSR , [InstrStage<4, [IU2]>]>, - InstrItinData<IIC_SprMTMSR , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_SprMTSR , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_SprMFCR , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_SprMFMSR , [InstrStage<3, [IU2]>]>, - InstrItinData<IIC_SprMFSPR , [InstrStage<4, [IU2]>]>, - InstrItinData<IIC_SprMFTB , [InstrStage<5, [IU2]>]>, - InstrItinData<IIC_SprMTSPR , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, - InstrItinData<IIC_FPGeneral , [InstrStage<5, [FPU1]>]>, - InstrItinData<IIC_FPAddSub , [InstrStage<5, [FPU1]>]>, - InstrItinData<IIC_FPCompare , [InstrStage<5, [FPU1]>]>, - InstrItinData<IIC_FPDivD , [InstrStage<35, [FPU1]>]>, - InstrItinData<IIC_FPDivS , [InstrStage<21, [FPU1]>]>, - InstrItinData<IIC_FPFused , [InstrStage<5, [FPU1]>]>, - InstrItinData<IIC_FPRes , [InstrStage<14, [FPU1]>]>, - InstrItinData<IIC_VecGeneral , [InstrStage<1, [VIU1]>]>, - InstrItinData<IIC_VecFP , [InstrStage<4, [VFPU]>]>, - InstrItinData<IIC_VecFPCompare, [InstrStage<2, [VFPU]>]>, - InstrItinData<IIC_VecComplex , [InstrStage<4, [VIU2]>]>, - InstrItinData<IIC_VecPerm , [InstrStage<2, [VPU]>]>, - InstrItinData<IIC_VecFPRound , [InstrStage<4, [VIU1]>]>, - InstrItinData<IIC_VecVSL , [InstrStage<2, [VPU]>]>, - InstrItinData<IIC_VecVSR , [InstrStage<2, [VPU]>]> + [G4P_IU1, G4P_IU2, G4P_IU3, G4P_IU4, G4P_BPU, G4P_SLU, G4P_FPU1, + G4P_VFPU, G4P_VIU1, G4P_VIU2, G4P_VPU], [], [ + InstrItinData<IIC_IntSimple , [InstrStage<1, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_IntCompare , [InstrStage<1, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_IntDivW , [InstrStage<23, [G4P_IU2]>]>, + InstrItinData<IIC_IntMFFS , [InstrStage<5, [G4P_FPU1]>]>, + InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [G4P_VFPU]>]>, + InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [G4P_FPU1]>]>, + InstrItinData<IIC_IntMulHW , [InstrStage<4, [G4P_IU2]>]>, + InstrItinData<IIC_IntMulHWU , [InstrStage<4, [G4P_IU2]>]>, + InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4P_IU2]>]>, + InstrItinData<IIC_IntRotate , [InstrStage<1, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_IntShift , [InstrStage<2, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_BrB , [InstrStage<1, [G4P_BPU]>]>, + InstrItinData<IIC_BrCR , [InstrStage<2, [G4P_IU2]>]>, + InstrItinData<IIC_BrMCR , [InstrStage<2, [G4P_IU2]>]>, + InstrItinData<IIC_BrMCRX , [InstrStage<2, [G4P_IU2]>]>, + InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLoad , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStStore , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStDSS , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStICBI , [InstrStage<3, [G4P_IU2]>]>, + InstrItinData<IIC_LdStSTFD , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLFD , [InstrStage<4, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLFDU , [InstrStage<4, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLHA , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLHAU , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLMW , [InstrStage<37, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLWA , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStSTD , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_LdStSync , [InstrStage<35, [G4P_SLU]>]>, + InstrItinData<IIC_SprISYNC , [InstrStage<0, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_SprMFSR , [InstrStage<4, [G4P_IU2]>]>, + InstrItinData<IIC_SprMTMSR , [InstrStage<2, [G4P_IU2]>]>, + InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4P_IU2]>]>, + InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G4P_SLU]>]>, + InstrItinData<IIC_SprMFCR , [InstrStage<2, [G4P_IU2]>]>, + InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G4P_IU2]>]>, + InstrItinData<IIC_SprMFSPR , [InstrStage<4, [G4P_IU2]>]>, + InstrItinData<IIC_SprMFTB , [InstrStage<5, [G4P_IU2]>]>, + InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4P_IU2]>]>, + InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4P_IU2]>]>, + InstrItinData<IIC_SprRFI , [InstrStage<1, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_SprSC , [InstrStage<0, [G4P_IU1, G4P_IU2, + G4P_IU3, G4P_IU4]>]>, + InstrItinData<IIC_FPGeneral , [InstrStage<5, [G4P_FPU1]>]>, + InstrItinData<IIC_FPAddSub , [InstrStage<5, [G4P_FPU1]>]>, + InstrItinData<IIC_FPCompare , [InstrStage<5, [G4P_FPU1]>]>, + InstrItinData<IIC_FPDivD , [InstrStage<35, [G4P_FPU1]>]>, + InstrItinData<IIC_FPDivS , [InstrStage<21, [G4P_FPU1]>]>, + InstrItinData<IIC_FPFused , [InstrStage<5, [G4P_FPU1]>]>, + InstrItinData<IIC_FPRes , [InstrStage<14, [G4P_FPU1]>]>, + InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4P_VIU1]>]>, + InstrItinData<IIC_VecFP , [InstrStage<4, [G4P_VFPU]>]>, + InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G4P_VFPU]>]>, + InstrItinData<IIC_VecComplex , [InstrStage<4, [G4P_VIU2]>]>, + InstrItinData<IIC_VecPerm , [InstrStage<2, [G4P_VPU]>]>, + InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4P_VIU1]>]>, + InstrItinData<IIC_VecVSL , [InstrStage<2, [G4P_VPU]>]>, + InstrItinData<IIC_VecVSR , [InstrStage<2, [G4P_VPU]>]> ]>; diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td index a97647acb5..2329e58b1c 100644 --- a/lib/Target/PowerPC/PPCScheduleG5.td +++ b/lib/Target/PowerPC/PPCScheduleG5.td @@ -11,90 +11,103 @@ // //===----------------------------------------------------------------------===// +def G5_BPU : FuncUnit; // Branch unit +def G5_SLU : FuncUnit; // Store/load unit +def G5_SRU : FuncUnit; // special register unit +def G5_IU1 : FuncUnit; // integer unit 1 (simple) +def G5_IU2 : FuncUnit; // integer unit 2 (complex) +def G5_FPU1 : FuncUnit; // floating point unit 1 +def G5_FPU2 : FuncUnit; // floating point unit 2 +def G5_VPU : FuncUnit; // vector permutation unit +def G5_VIU1 : FuncUnit; // vector integer unit 1 (simple) +def G5_VIU2 : FuncUnit; // vector integer unit 2 (complex) +def G5_VFPU : FuncUnit; // vector floating point unit + def G5Itineraries : ProcessorItineraries< - [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [ - InstrItinData<IIC_IntSimple , [InstrStage<2, [IU1, IU2]>]>, - InstrItinData<IIC_IntGeneral , [InstrStage<2, [IU1, IU2]>]>, - InstrItinData<IIC_IntCompare , [InstrStage<3, [IU1, IU2]>]>, - InstrItinData<IIC_IntDivD , [InstrStage<68, [IU1]>]>, - InstrItinData<IIC_IntDivW , [InstrStage<36, [IU1]>]>, - InstrItinData<IIC_IntMFFS , [InstrStage<6, [IU2]>]>, - InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [VFPU]>]>, - InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>, - InstrItinData<IIC_IntMulHD , [InstrStage<7, [IU1, IU2]>]>, - InstrItinData<IIC_IntMulHW , [InstrStage<5, [IU1, IU2]>]>, - InstrItinData<IIC_IntMulHWU , [InstrStage<5, [IU1, IU2]>]>, - InstrItinData<IIC_IntMulLI , [InstrStage<4, [IU1, IU2]>]>, - InstrItinData<IIC_IntRFID , [InstrStage<1, [IU2]>]>, - InstrItinData<IIC_IntRotateD , [InstrStage<2, [IU1, IU2]>]>, - InstrItinData<IIC_IntRotateDI , [InstrStage<2, [IU1, IU2]>]>, - InstrItinData<IIC_IntRotate , [InstrStage<4, [IU1, IU2]>]>, - InstrItinData<IIC_IntShift , [InstrStage<2, [IU1, IU2]>]>, - InstrItinData<IIC_IntTrapD , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_IntTrapW , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>, - InstrItinData<IIC_BrCR , [InstrStage<4, [BPU]>]>, - InstrItinData<IIC_BrMCR , [InstrStage<2, [BPU]>]>, - InstrItinData<IIC_BrMCRX , [InstrStage<3, [BPU]>]>, - InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLoad , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStStore , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStDSS , [InstrStage<10, [SLU]>]>, - InstrItinData<IIC_LdStICBI , [InstrStage<40, [SLU]>]>, - InstrItinData<IIC_LdStSTFD , [InstrStage<4, [SLU]>]>, - InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [SLU]>]>, - InstrItinData<IIC_LdStLD , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLDU , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLDARX , [InstrStage<11, [SLU]>]>, - InstrItinData<IIC_LdStLFD , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLFDU , [InstrStage<5, [SLU]>]>, - InstrItinData<IIC_LdStLHA , [InstrStage<5, [SLU]>]>, - InstrItinData<IIC_LdStLHAU , [InstrStage<5, [SLU]>]>, - InstrItinData<IIC_LdStLMW , [InstrStage<64, [SLU]>]>, - InstrItinData<IIC_LdStLVecX , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStLWA , [InstrStage<5, [SLU]>]>, - InstrItinData<IIC_LdStLWARX , [InstrStage<11, [SLU]>]>, - InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work - InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [SLU]>]>, - InstrItinData<IIC_LdStSTD , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTDU , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [SLU]>]>, - InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [SLU]>]>, - InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [SLU]>]>, - InstrItinData<IIC_LdStSync , [InstrStage<35, [SLU]>]>, - InstrItinData<IIC_SprISYNC , [InstrStage<40, [SLU]>]>, // needs work - InstrItinData<IIC_SprMFSR , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_SprMTMSR , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_SprMTSR , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SLU]>]>, - InstrItinData<IIC_SprMFCR , [InstrStage<2, [IU2]>]>, - InstrItinData<IIC_SprMFMSR , [InstrStage<3, [IU2]>]>, - InstrItinData<IIC_SprMFSPR , [InstrStage<3, [IU2]>]>, - InstrItinData<IIC_SprMFTB , [InstrStage<10, [IU2]>]>, - InstrItinData<IIC_SprMTSPR , [InstrStage<8, [IU2]>]>, - InstrItinData<IIC_SprSC , [InstrStage<1, [IU2]>]>, - InstrItinData<IIC_FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>, - InstrItinData<IIC_FPAddSub , [InstrStage<6, [FPU1, FPU2]>]>, - InstrItinData<IIC_FPCompare , [InstrStage<8, [FPU1, FPU2]>]>, - InstrItinData<IIC_FPDivD , [InstrStage<33, [FPU1, FPU2]>]>, - InstrItinData<IIC_FPDivS , [InstrStage<33, [FPU1, FPU2]>]>, - InstrItinData<IIC_FPFused , [InstrStage<6, [FPU1, FPU2]>]>, - InstrItinData<IIC_FPRes , [InstrStage<6, [FPU1, FPU2]>]>, - InstrItinData<IIC_FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>, - InstrItinData<IIC_VecGeneral , [InstrStage<2, [VIU1]>]>, - InstrItinData<IIC_VecFP , [InstrStage<8, [VFPU]>]>, - InstrItinData<IIC_VecFPCompare, [InstrStage<2, [VFPU]>]>, - InstrItinData<IIC_VecComplex , [InstrStage<5, [VIU2]>]>, - InstrItinData<IIC_VecPerm , [InstrStage<3, [VPU]>]>, - InstrItinData<IIC_VecFPRound , [InstrStage<8, [VFPU]>]>, - InstrItinData<IIC_VecVSL , [InstrStage<2, [VIU1]>]>, - InstrItinData<IIC_VecVSR , [InstrStage<3, [VPU]>]> + [G5_IU1, G5_IU2, G5_SLU, G5_BPU, G5_FPU1, G5_FPU2, + G5_VFPU, G5_VIU1, G5_VIU2, G5_VPU], [], [ + InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>, + InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>, + InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>, + InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>, + InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntMulHWU , [InstrStage<5, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntMulLI , [InstrStage<4, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>, + InstrItinData<IIC_IntRotateD , [InstrStage<2, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntRotateDI , [InstrStage<2, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntRotate , [InstrStage<4, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntShift , [InstrStage<2, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntTrapD , [InstrStage<1, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_IntTrapW , [InstrStage<1, [G5_IU1, G5_IU2]>]>, + InstrItinData<IIC_BrB , [InstrStage<1, [G5_BPU]>]>, + InstrItinData<IIC_BrCR , [InstrStage<4, [G5_BPU]>]>, + InstrItinData<IIC_BrMCR , [InstrStage<2, [G5_BPU]>]>, + InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>, + InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>, + InstrItinData<IIC_LdStICBI , [InstrStage<40, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTFD , [InstrStage<4, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>, + InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>, + InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>, + InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStLWARX , [InstrStage<11, [G5_SLU]>]>, + InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [G5_SLU]>]>, // needs work + InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>, + InstrItinData<IIC_LdStSync , [InstrStage<35, [G5_SLU]>]>, + InstrItinData<IIC_SprISYNC , [InstrStage<40, [G5_SLU]>]>, // needs work + InstrItinData<IIC_SprMFSR , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_SprMTMSR , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>, + InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>, + InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>, + InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>, + InstrItinData<IIC_SprMTSPR , [InstrStage<8, [G5_IU2]>]>, + InstrItinData<IIC_SprSC , [InstrStage<1, [G5_IU2]>]>, + InstrItinData<IIC_FPGeneral , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPAddSub , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPCompare , [InstrStage<8, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPDivD , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPSqrt , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>, + InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>, + InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>, + InstrItinData<IIC_VecComplex , [InstrStage<5, [G5_VIU2]>]>, + InstrItinData<IIC_VecPerm , [InstrStage<3, [G5_VPU]>]>, + InstrItinData<IIC_VecFPRound , [InstrStage<8, [G5_VFPU]>]>, + InstrItinData<IIC_VecVSL , [InstrStage<2, [G5_VIU1]>]>, + InstrItinData<IIC_VecVSR , [InstrStage<3, [G5_VPU]>]> ]>; // ===---------------------------------------------------------------------===// -// e5500 machine model for scheduling and other instruction cost heuristics. +// G5 machine model for scheduling and other instruction cost heuristics. def G5Model : SchedMachineModel { let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle. |