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authorKay Tiong Khoo <kkhoo@perfwizard.com>2013-02-12 00:19:12 +0000
committerKay Tiong Khoo <kkhoo@perfwizard.com>2013-02-12 00:19:12 +0000
commit6c3daabc3ee51a8fcb804e0f110f01e59e0e6d61 (patch)
treefcab8b8339070a35ecf1fc7d2418566b66876428
parentc951003faf4d475d221f5e839971673d2350b983 (diff)
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Added 0x0D to 2-byte opcode extension table for prefetch* variants
Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86Instr3DNow.td6
-rw-r--r--utils/TableGen/X86RecognizableInstr.cpp1
2 files changed, 3 insertions, 4 deletions
diff --git a/lib/Target/X86/X86Instr3DNow.td b/lib/Target/X86/X86Instr3DNow.td
index 54b91c3edb..bb362f5c7b 100644
--- a/lib/Target/X86/X86Instr3DNow.td
+++ b/lib/Target/X86/X86Instr3DNow.td
@@ -87,12 +87,10 @@ defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw">;
def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
- "prefetch $addr", []>;
+ "prefetch\t$addr", []>;
-// FIXME: Diassembler gets a bogus decode conflict.
-let isAsmParserOnly = 1 in
def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
- "prefetchw $addr", []>;
+ "prefetchw\t$addr", []>;
// "3DNowA" instructions
defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">;
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index b99a6eb87e..b00f7ea2ba 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -119,6 +119,7 @@ namespace X86Local {
#define TWO_BYTE_EXTENSION_TABLES \
EXTENSION_TABLE(00) \
EXTENSION_TABLE(01) \
+ EXTENSION_TABLE(0d) \
EXTENSION_TABLE(18) \
EXTENSION_TABLE(71) \
EXTENSION_TABLE(72) \