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| author | Andrew Trick <atrick@apple.com> | 2013-12-28 21:57:05 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-12-28 21:57:05 +0000 |
| commit | 6c9712fecb661523ee85c0fd1a1a0833754440f8 (patch) | |
| tree | 7703c9eeaa5de72f289d0e41eacd4b9853684475 | |
| parent | d3f8d6e0a011019939f37a481a58b25b1cdbb8fb (diff) | |
| download | llvm-6c9712fecb661523ee85c0fd1a1a0833754440f8.tar.gz llvm-6c9712fecb661523ee85c0fd1a1a0833754440f8.tar.bz2 llvm-6c9712fecb661523ee85c0fd1a1a0833754440f8.tar.xz | |
New machine model for cortex-a9. Schedule for resources and latency.
Schedule more conservatively to account for stalls on floating point
resources and latency. Use the AGU resource to model latency stalls
since it's shared between FP and LD/ST instructions. This might not be
completely accurate but should work well in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198125 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 10 | ||||
| -rw-r--r-- | test/CodeGen/ARM/saxpy10-a9.ll | 20 |
2 files changed, 18 insertions, 12 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index e4c2c753ae..9a1d222756 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -1902,14 +1902,20 @@ def CortexA9Model : SchedMachineModel { //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available. +// +// The AGU unit has BufferSize=1 so that the latency between operations +// that use it are considered to stall other operations. +// +// The FP unit has BufferSize=0 so that it is a hard dispatch +// hazard. No instruction may be dispatched while the unit is reserved. let SchedModel = CortexA9Model in { def A9UnitALU : ProcResource<2>; def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; } -def A9UnitAGU : ProcResource<1>; +def A9UnitAGU : ProcResource<1> { let BufferSize = 1; } def A9UnitLS : ProcResource<1>; -def A9UnitFP : ProcResource<1> { let BufferSize = 1; } +def A9UnitFP : ProcResource<1> { let BufferSize = 0; } def A9UnitB : ProcResource<1>; //===----------------------------------------------------------------------===// diff --git a/test/CodeGen/ARM/saxpy10-a9.ll b/test/CodeGen/ARM/saxpy10-a9.ll index 1102800dce..f8f5e18fcf 100644 --- a/test/CodeGen/ARM/saxpy10-a9.ll +++ b/test/CodeGen/ARM/saxpy10-a9.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -disable-post-ra -misched-bench -scheditins=false | FileCheck %s +; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -misched-postra -misched-bench -scheditins=false | FileCheck %s ; ; Test MI-Sched suppory latency based stalls on in in-order pipeline ; using the new machine model. @@ -15,43 +15,43 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK: vldr ; CHECK: vldr ; CHECK: vldr -; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vldr +; CHECK-NEXT: vldr +; CHECK-NEXT: vadd ; CHECK-NEXT: vmul +; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd -; CHECK-NEXT: vldr -; CHECK-NEXT: vldr ; CHECK-NEXT: vmul +; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr -; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vadd -; CHECK-NEXT: vldr ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd +; CHECK-NEXT: vldr +; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vadd |