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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-08-30 22:50:36 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-08-30 22:50:36 +0000 |
| commit | 6d1e29d2f203093e3e03f15173c0f36637d3afe3 (patch) | |
| tree | df6863a1b8a797edbfcd344429626376c3ff4e89 | |
| parent | f523b3e0878ea47e72b7d880b8fd18a33636fbde (diff) | |
| download | llvm-6d1e29d2f203093e3e03f15173c0f36637d3afe3.tar.gz llvm-6d1e29d2f203093e3e03f15173c0f36637d3afe3.tar.bz2 llvm-6d1e29d2f203093e3e03f15173c0f36637d3afe3.tar.xz | |
Expand MOVi32imm in ARM mode after regalloc. This provides
scheduling opportunities (extra instruction can go in between
MOVT / MOVW pair removing the stall).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112546 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 285674d64d..4033d34333 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -167,6 +167,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { break; } + case ARM::MOVi32imm: case ARM::t2MOVi32imm: { unsigned PredReg = 0; ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); @@ -175,9 +176,13 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { const MachineOperand &MO = MI.getOperand(1); MachineInstrBuilder LO16, HI16; - LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::t2MOVi16), + LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(Opcode == ARM::MOVi32imm ? + ARM::MOVi16 : ARM::t2MOVi16), DstReg); - HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::t2MOVTi16)) + HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(Opcode == ARM::MOVi32imm ? + ARM::MOVTi16 : ARM::t2MOVTi16)) .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) .addReg(DstReg); |