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author | Bill Wendling <isanbard@gmail.com> | 2010-08-08 01:49:35 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2010-08-08 01:49:35 +0000 |
commit | 73739d0bf19af3944aff6afaea2c4eda61061652 (patch) | |
tree | dc3396c783f311ec6d00f0012a1e801f072a8c31 | |
parent | a5c4cc5f34c0d211fbe639168fa01c6364c9b888 (diff) | |
download | llvm-73739d0bf19af3944aff6afaea2c4eda61061652.tar.gz llvm-73739d0bf19af3944aff6afaea2c4eda61061652.tar.bz2 llvm-73739d0bf19af3944aff6afaea2c4eda61061652.tar.xz |
Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/Target/Target.td | 1 | ||||
-rw-r--r-- | include/llvm/Target/TargetInstrDesc.h | 8 | ||||
-rw-r--r-- | utils/TableGen/CodeGenInstruction.cpp | 1 | ||||
-rw-r--r-- | utils/TableGen/CodeGenInstruction.h | 1 | ||||
-rw-r--r-- | utils/TableGen/InstrInfoEmitter.cpp | 1 |
5 files changed, 11 insertions, 1 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index ad1a816a95..809e088e2b 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -198,6 +198,7 @@ class Instruction { bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? bit isIndirectBranch = 0; // Is this instruction an indirect branch? + bit isCompare = 0; // Is this instruction a comparison instruction? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h index 8f0a6cb1a6..6a08e8f24c 100644 --- a/include/llvm/Target/TargetInstrDesc.h +++ b/include/llvm/Target/TargetInstrDesc.h @@ -105,6 +105,7 @@ namespace TID { IndirectBranch, Predicable, NotDuplicable, + Compare, DelaySlot, FoldableAsLoad, MayLoad, @@ -315,7 +316,7 @@ public: bool isIndirectBranch() const { return Flags & (1 << TID::IndirectBranch); } - + /// isConditionalBranch - Return true if this is a branch which may fall /// through to the next instruction or may transfer control flow to some other /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more @@ -340,6 +341,11 @@ public: return Flags & (1 << TID::Predicable); } + /// isCompare - Return true if this instruction is a comparison. + bool isCompare() const { + return Flags & (1 << TID::Compare); + } + /// isNotDuplicable - Return true if this instruction cannot be safely /// duplicated. For example, if the instruction has a unique labels attached /// to it, duplicating it would cause multiple definition errors. diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index 35b54a5427..01a1fe11f5 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -102,6 +102,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) isReturn = R->getValueAsBit("isReturn"); isBranch = R->getValueAsBit("isBranch"); isIndirectBranch = R->getValueAsBit("isIndirectBranch"); + isCompare = R->getValueAsBit("isCompare"); isBarrier = R->getValueAsBit("isBarrier"); isCall = R->getValueAsBit("isCall"); canFoldAsLoad = R->getValueAsBit("canFoldAsLoad"); diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h index 946c2d01a5..b02d0d38f9 100644 --- a/utils/TableGen/CodeGenInstruction.h +++ b/utils/TableGen/CodeGenInstruction.h @@ -123,6 +123,7 @@ namespace llvm { bool isReturn; bool isBranch; bool isIndirectBranch; + bool isCompare; bool isBarrier; bool isCall; bool canFoldAsLoad; diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index f28af1589d..4d3aa5e621 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -270,6 +270,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, if (Inst.isReturn) OS << "|(1<<TID::Return)"; if (Inst.isBranch) OS << "|(1<<TID::Branch)"; if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)"; + if (Inst.isCompare) OS << "|(1<<TID::Compare)"; if (Inst.isBarrier) OS << "|(1<<TID::Barrier)"; if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)"; if (Inst.isCall) OS << "|(1<<TID::Call)"; |