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authorCraig Topper <craig.topper@gmail.com>2013-07-15 06:39:13 +0000
committerCraig Topper <craig.topper@gmail.com>2013-07-15 06:39:13 +0000
commit787e71df693e94cc512f3e439bf91609a8ec9bae (patch)
tree56b020bd3a6fda52f472b97f75876052bee34a00
parent793fd8d0d6d18d3b6057fce8e8f55269cf34400c (diff)
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Make some arrays 'static const'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186307 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/R600/AMDGPUISelLowering.cpp2
-rw-r--r--lib/Target/R600/AMDILISelLowering.cpp8
-rw-r--r--lib/Target/R600/R600ControlFlowFinalizer.cpp2
-rw-r--r--lib/Target/R600/SIInstrInfo.cpp10
4 files changed, 11 insertions, 11 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 3629d74bae..c9df89c2d7 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -78,7 +78,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
setOperationAction(ISD::UREM, MVT::i32, Expand);
- int types[] = {
+ static const int types[] = {
(int)MVT::v2i32,
(int)MVT::v4i32
};
diff --git a/lib/Target/R600/AMDILISelLowering.cpp b/lib/Target/R600/AMDILISelLowering.cpp
index 95e785b7a1..970787ef31 100644
--- a/lib/Target/R600/AMDILISelLowering.cpp
+++ b/lib/Target/R600/AMDILISelLowering.cpp
@@ -39,7 +39,7 @@ using namespace llvm;
// TargetLowering Class Implementation Begins
//===----------------------------------------------------------------------===//
void AMDGPUTargetLowering::InitAMDILLowering() {
- int types[] = {
+ static const int types[] = {
(int)MVT::i8,
(int)MVT::i16,
(int)MVT::i32,
@@ -58,19 +58,19 @@ void AMDGPUTargetLowering::InitAMDILLowering() {
(int)MVT::v2i64
};
- int IntTypes[] = {
+ static const int IntTypes[] = {
(int)MVT::i8,
(int)MVT::i16,
(int)MVT::i32,
(int)MVT::i64
};
- int FloatTypes[] = {
+ static const int FloatTypes[] = {
(int)MVT::f32,
(int)MVT::f64
};
- int VectorTypes[] = {
+ static const int VectorTypes[] = {
(int)MVT::v2i8,
(int)MVT::v4i8,
(int)MVT::v2i16,
diff --git a/lib/Target/R600/R600ControlFlowFinalizer.cpp b/lib/Target/R600/R600ControlFlowFinalizer.cpp
index 932a6a7243..1cd0ac38a2 100644
--- a/lib/Target/R600/R600ControlFlowFinalizer.cpp
+++ b/lib/Target/R600/R600ControlFlowFinalizer.cpp
@@ -172,7 +172,7 @@ private:
}
void getLiteral(MachineInstr *MI, std::vector<int64_t> &Lits) const {
- unsigned LiteralRegs[] = {
+ static const unsigned LiteralRegs[] = {
AMDGPU::ALU_LITERAL_X,
AMDGPU::ALU_LITERAL_Y,
AMDGPU::ALU_LITERAL_Z,
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
index cb582a6c16..551ae8683e 100644
--- a/lib/Target/R600/SIInstrInfo.cpp
+++ b/lib/Target/R600/SIInstrInfo.cpp
@@ -42,27 +42,27 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// never be necessary.
assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
- const int16_t Sub0_15[] = {
+ static const int16_t Sub0_15[] = {
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
};
- const int16_t Sub0_7[] = {
+ static const int16_t Sub0_7[] = {
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
};
- const int16_t Sub0_3[] = {
+ static const int16_t Sub0_3[] = {
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
};
- const int16_t Sub0_2[] = {
+ static const int16_t Sub0_2[] = {
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
};
- const int16_t Sub0_1[] = {
+ static const int16_t Sub0_1[] = {
AMDGPU::sub0, AMDGPU::sub1, 0
};