diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-12 20:02:50 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-12 20:02:50 +0000 |
| commit | 79628e92e1f903d50340d4cd3d1ea8c5fff63a87 (patch) | |
| tree | 65268e66fbc19c9564ae383b5e53b3074d20389d | |
| parent | c513309224611d662a8de51f81216164f5954a30 (diff) | |
| download | llvm-79628e92e1f903d50340d4cd3d1ea8c5fff63a87.tar.gz llvm-79628e92e1f903d50340d4cd3d1ea8c5fff63a87.tar.bz2 llvm-79628e92e1f903d50340d4cd3d1ea8c5fff63a87.tar.xz | |
Fix decoding of ARM-mode STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 3 |
3 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index eb613cdda7..f666f4ec73 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -664,6 +664,7 @@ class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{7-4} = op; let Inst{3-0} = addr{3-0}; // imm3_0/Rm + let DecoderMethod = "DecodeAddrMode3Instruction"; } // Pre-indexed stores diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 44acbdc705..8641d0b26a 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2365,6 +2365,7 @@ def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{3-0} = addr{3-0}; // imm3_0/Rm let AsmMatchConverter = "cvtStWriteBackRegAddrMode3"; + let DecoderMethod = "DecodeAddrMode3Instruction"; } def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), @@ -2381,6 +2382,7 @@ def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), let Inst{19-16} = addr; let Inst{11-8} = offset{7-4}; // imm7_4/zero let Inst{3-0} = offset{3-0}; // imm3_0/Rm + let DecoderMethod = "DecodeAddrMode3Instruction"; } let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 7de0c236ac..b3db84947d 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1090,6 +1090,9 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST: + case ARM::STRH: + case ARM::STRH_PRE: + case ARM::STRH_POST: if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; break; |