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authorJim Grosbach <grosbach@apple.com>2009-09-11 20:13:17 +0000
committerJim Grosbach <grosbach@apple.com>2009-09-11 20:13:17 +0000
commit82b3c2e40417098f9af0c33150c4b1c66ae1747c (patch)
tree29733bae380638d681c2175d5bfbcafb1d15e490
parente11a8f565c6a019ddc54667227be9c4d8f117473 (diff)
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Revert array initialization regclass change so that the initialization stays static, not runtime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81560 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMBaseRegisterInfo.cpp44
1 files changed, 20 insertions, 24 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 908819cd47..ca3e5097f9 100644
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -164,46 +164,42 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const TargetRegisterClass* const *
ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
- ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
- ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
- ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
0
};
static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
- ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
- ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::tGPRRegisterClass,
- ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
+ &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
0
};
static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
- ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
- ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
- ARM::GPRRegisterClass, ARM::GPRRegisterClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
0
};
static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
- ARM::GPRRegisterClass, ARM::tGPRRegisterClass, ARM::tGPRRegisterClass,
- ARM::tGPRRegisterClass, ARM::tGPRRegisterClass, ARM::GPRRegisterClass,
- ARM::GPRRegisterClass, ARM::GPRRegisterClass,
+ &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
+ &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
+ &ARM::GPRRegClass, &ARM::GPRRegClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+ &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
0
};