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| author | Eli Friedman <eli.friedman@gmail.com> | 2012-11-15 22:44:27 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2012-11-15 22:44:27 +0000 |
| commit | 846ce8ea67362d8b6d93ebae66f23e3c68dce9df (patch) | |
| tree | 8557abf21fd844337721b20f92738a5ecb846e20 | |
| parent | a5a241cf3145e28d1ef5e69c65cc040c5533ba69 (diff) | |
| download | llvm-846ce8ea67362d8b6d93ebae66f23e3c68dce9df.tar.gz llvm-846ce8ea67362d8b6d93ebae66f23e3c68dce9df.tar.bz2 llvm-846ce8ea67362d8b6d93ebae66f23e3c68dce9df.tar.xz | |
Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing
case to vector legalization so this actually works.
Patch by Pete Couperus. Fixes PR12540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/neon_fpconv.ll | 9 |
3 files changed, 12 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 22f8d51ab2..3250133a67 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -221,6 +221,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { case ISD::FRINT: case ISD::FNEARBYINT: case ISD::FFLOOR: + case ISD::FP_ROUND: case ISD::FMA: case ISD::SIGN_EXTEND_INREG: QueryType = Node->getValueType(0); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index c2e084816f..f53d664268 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -544,6 +544,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); + setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); + setTargetDAGCombine(ISD::INTRINSIC_VOID); setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); diff --git a/test/CodeGen/ARM/neon_fpconv.ll b/test/CodeGen/ARM/neon_fpconv.ll new file mode 100644 index 0000000000..f80ea3e349 --- /dev/null +++ b/test/CodeGen/ARM/neon_fpconv.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32. +define <2 x float> @vtrunc(<2 x double> %a) { +; CHECK: vcvt.f32.f64 [[S0:s[0-9]+]], [[D0:d[0-9]+]] +; CHECK: vcvt.f32.f64 [[S1:s[0-9]+]], [[D1:d[0-9]+]] + %vt = fptrunc <2 x double> %a to <2 x float> + ret <2 x float> %vt +} |