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| author | Joey Gouly <joey.gouly@arm.com> | 2013-09-18 09:46:49 +0000 |
|---|---|---|
| committer | Joey Gouly <joey.gouly@arm.com> | 2013-09-18 09:46:49 +0000 |
| commit | 8634b0ee47be832fbf3fd6ceebb8ac9104106bc2 (patch) | |
| tree | 5e9c67e20037a82370e3109f5aff1c208ea764a1 | |
| parent | a4d46d7fc6431ec3576839f11cb61862b784cb3e (diff) | |
| download | llvm-8634b0ee47be832fbf3fd6ceebb8ac9104106bc2.tar.gz llvm-8634b0ee47be832fbf3fd6ceebb8ac9104106bc2.tar.bz2 llvm-8634b0ee47be832fbf3fd6ceebb8ac9104106bc2.tar.xz | |
'svn add' the test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190929 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/MC/ARM/crc32-thumb.s | 23 | ||||
| -rw-r--r-- | test/MC/ARM/crc32.s | 23 | ||||
| -rw-r--r-- | test/MC/ARM/invalid-crc32.s | 16 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/crc32-thumb.txt | 15 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/crc32.txt | 15 |
5 files changed, 92 insertions, 0 deletions
diff --git a/test/MC/ARM/crc32-thumb.s b/test/MC/ARM/crc32-thumb.s new file mode 100644 index 0000000000..e0f39c31c9 --- /dev/null +++ b/test/MC/ARM/crc32-thumb.s @@ -0,0 +1,23 @@ +@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 + crc32b r0, r1, r2 + crc32h r0, r1, r2 + crc32w r0, r1, r2 + +@ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0] +@ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0] +@ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0] +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 + + crc32cb r0, r1, r2 + crc32ch r0, r1, r2 + crc32cw r0, r1, r2 + +@ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0] +@ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0] +@ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0] +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 diff --git a/test/MC/ARM/crc32.s b/test/MC/ARM/crc32.s new file mode 100644 index 0000000000..eeb6fe8939 --- /dev/null +++ b/test/MC/ARM/crc32.s @@ -0,0 +1,23 @@ +@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 + crc32b r0, r1, r2 + crc32h r0, r1, r2 + crc32w r0, r1, r2 + +@ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1] +@ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1] +@ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1] +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 + + crc32cb r0, r1, r2 + crc32ch r0, r1, r2 + crc32cw r0, r1, r2 + +@ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1] +@ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1] +@ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1] +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 diff --git a/test/MC/ARM/invalid-crc32.s b/test/MC/ARM/invalid-crc32.s new file mode 100644 index 0000000000..a541002acb --- /dev/null +++ b/test/MC/ARM/invalid-crc32.s @@ -0,0 +1,16 @@ +@ RUN: not llvm-mc -triple=armv8 -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck %s + + crc32cbeq r0, r1, r2 + crc32bne r0, r1, r2 + crc32chcc r0, r1, r2 + crc32hpl r0, r1, r2 + crc32cwgt r0, r1, r2 + crc32wle r0, r1, r2 + +@ CHECK: error: instruction 'crc32cb' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32b' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32ch' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32h' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32cw' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32w' is not predicable, but condition code specified diff --git a/test/MC/Disassembler/ARM/crc32-thumb.txt b/test/MC/Disassembler/ARM/crc32-thumb.txt new file mode 100644 index 0000000000..2f83b58fd4 --- /dev/null +++ b/test/MC/Disassembler/ARM/crc32-thumb.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv8 2>&1 | FileCheck %s + +# CHECK: crc32b r0, r1, r2 +# CHECK: crc32h r0, r1, r2 +# CHECK: crc32w r0, r1, r2 +# CHECK: crc32cb r0, r1, r2 +# CHECK: crc32ch r0, r1, r2 +# CHECK: crc32cw r0, r1, r2 + +0xc1 0xfa 0x82 0xf0 +0xc1 0xfa 0x92 0xf0 +0xc1 0xfa 0xa2 0xf0 +0xd1 0xfa 0x82 0xf0 +0xd1 0xfa 0x92 0xf0 +0xd1 0xfa 0xa2 0xf0 diff --git a/test/MC/Disassembler/ARM/crc32.txt b/test/MC/Disassembler/ARM/crc32.txt new file mode 100644 index 0000000000..17bb03220e --- /dev/null +++ b/test/MC/Disassembler/ARM/crc32.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=armv8 2>&1 | FileCheck %s + +# CHECK: crc32b r0, r1, r2 +# CHECK: crc32h r0, r1, r2 +# CHECK: crc32w r0, r1, r2 +# CHECK: crc32cb r0, r1, r2 +# CHECK: crc32ch r0, r1, r2 +# CHECK: crc32cw r0, r1, r2 + +0x42 0x00 0x01 0xe1 +0x42 0x00 0x21 0xe1 +0x42 0x00 0x41 0xe1 +0x42 0x02 0x01 0xe1 +0x42 0x02 0x21 0xe1 +0x42 0x02 0x41 0xe1 |