Now that the ISel is available, it's possible to create a default instruction

scheduler creator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29452 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 30 insertions, 17 deletions

diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 17212c45f7..5c39b505fe 100644
--- a/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -38,6 +38,7 @@ namespace {
       (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL);
       (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL);
       (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL);
+      (void) llvm::createDefaultScheduler(NULL, NULL, NULL);
 
     }
   } ForceCodegenLinking; // Force link by creating a global definition.
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index a1214db8a8..dbf532818b 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -258,6 +258,11 @@ namespace llvm {
                                         SelectionDAG *DAG,
                                         MachineBasicBlock *BB);
                                         
+  /// createDefaultScheduler - This creates an instruction scheduler appropriate
+  /// for the target.
+  ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
+                                      SelectionDAG *DAG,
+                                      MachineBasicBlock *BB);
 }
 
 #endif
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 78179c9e2a..e5d024a892 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -41,6 +41,8 @@ public:
   MachineBasicBlock *BB;
 
   SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
+  
+  TargetLowering &getTargetLowering() { return TLI; }
 
   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 84daabbd63..3a1af95e81 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -68,7 +68,8 @@ namespace {
               cl::desc("Instruction schedulers available:"));
 
   static RegisterScheduler
-  defaultListDAGScheduler("default", "  Best scheduler for the target", NULL);
+  defaultListDAGScheduler("default", "  Best scheduler for the target",
+                          createDefaultScheduler);
 } // namespace
 
 namespace {
@@ -124,6 +125,24 @@ namespace {
 
 namespace llvm {
   //===--------------------------------------------------------------------===//
+  /// createDefaultScheduler - This creates an instruction scheduler appropriate
+  /// for the target.
+  ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
+                                      SelectionDAG *DAG,
+                                      MachineBasicBlock *BB) {
+    TargetLowering &TLI = IS->getTargetLowering();
+    
+    if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
+      return createTDListDAGScheduler(IS, DAG, BB);
+    } else {
+      assert(TLI.getSchedulingPreference() ==
+           TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
+      return createBURRListDAGScheduler(IS, DAG, BB);
+    }
+  }
+
+
+  //===--------------------------------------------------------------------===//
   /// FunctionLoweringInfo - This contains information that is global to a
   /// function that is used when lowering a region of the function.
   class FunctionLoweringInfo {
@@ -3614,22 +3633,8 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
                                                 RegisterScheduler::getDefault();
   
   if (!Ctor) {
-    if (std::string("default") == std::string(ISHeuristic)) {
-      if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
-        Ctor = RegisterScheduler::FindCtor("list-td");
-      else {
-        assert(TLI.getSchedulingPreference() ==
-             TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
-        Ctor = RegisterScheduler::FindCtor("list-burr");
-      }
-
-      assert(Ctor && "Default instruction scheduler not present");
-      if (!Ctor) Ctor = RegisterScheduler::FindCtor("none");
-    } else {
-      Ctor = RegisterScheduler::FindCtor(ISHeuristic);
-    }
-    
-     RegisterScheduler::setDefault(Ctor);
+    Ctor = RegisterScheduler::FindCtor(ISHeuristic);
+    RegisterScheduler::setDefault(Ctor);
   }
   
   assert(Ctor && "No instruction scheduler found");