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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-11-09 02:38:51 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-11-09 02:38:51 +0000 |
| commit | 95830221bd4877816adc6707eb34ca68c5a515d2 (patch) | |
| tree | 3a06f1281d43cd68c7baf0878c0aef34ee3c3e4a | |
| parent | ceb0d9c085492151f8e4538119bf3de29ff935c0 (diff) | |
| download | llvm-95830221bd4877816adc6707eb34ca68c5a515d2.tar.gz llvm-95830221bd4877816adc6707eb34ca68c5a515d2.tar.bz2 llvm-95830221bd4877816adc6707eb34ca68c5a515d2.tar.xz | |
[mips] Make sure there is a chain edge dependency between loads that read
formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194309 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/Mips/i64arg.ll | 14 | ||||
| -rw-r--r-- | test/CodeGen/Mips/tailcall.ll | 13 |
3 files changed, 25 insertions, 10 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 7a0e666ecf..5f82b4e69c 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -2650,9 +2650,11 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, // Create load nodes to retrieve arguments from the stack SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN, - MachinePointerInfo::getFixedStack(FI), - false, false, false, 0)); + SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN, + MachinePointerInfo::getFixedStack(FI), + false, false, false, 0); + InVals.push_back(Load); + OutChains.push_back(Load.getValue(1)); } } diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll index b038ad5bf7..5b2d135180 100644 --- a/test/CodeGen/Mips/i64arg.ll +++ b/test/CodeGen/Mips/i64arg.ll @@ -2,16 +2,16 @@ define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: -; CHECK: move $[[R1:[0-9]+]], $5 -; CHECK: move $[[R0:[0-9]+]], $4 -; CHECK: ori $6, ${{[0-9]+}}, 3855 -; CHECK: ori $7, ${{[0-9]+}}, 22136 -; CHECK: lw $25, %call16(ff1) +; CHECK-DAG: lw $[[R2:[0-9]+]], 80($sp) +; CHECK-DAG: lw $[[R3:[0-9]+]], 84($sp) +; CHECK-DAG: move $[[R1:[0-9]+]], $5 +; CHECK-DAG: move $[[R0:[0-9]+]], $4 +; CHECK-DAG: ori $6, ${{[0-9]+}}, 3855 +; CHECK-DAG: ori $7, ${{[0-9]+}}, 22136 +; CHECK-DAG: lw $25, %call16(ff1) ; CHECK: jalr tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind ; CHECK-DAG: lw $25, %call16(ff2) -; CHECK-DAG: lw $[[R2:[0-9]+]], 80($sp) -; CHECK-DAG: lw $[[R3:[0-9]+]], 84($sp) ; CHECK-DAG: move $4, $[[R2]] ; CHECK-DAG: move $5, $[[R3]] ; CHECK: jalr $25 diff --git a/test/CodeGen/Mips/tailcall.ll b/test/CodeGen/Mips/tailcall.ll index bcd33fca70..30f47abc06 100644 --- a/test/CodeGen/Mips/tailcall.ll +++ b/test/CodeGen/Mips/tailcall.ll @@ -243,3 +243,16 @@ entry: ret i32 %call } +; Check that there is a chain edge between the load and store nodes. +; +; PIC32-LABEL: caller14: +; PIC32: lw ${{[0-9]+}}, 16($sp) +; PIC32: sw $4, 16($sp) + +define void @caller14(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { +entry: + tail call void @callee14(i32 %e, i32 %b, i32 %c, i32 %d, i32 %a) + ret void +} + +declare void @callee14(i32, i32, i32, i32, i32) |