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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-22 11:51:06 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-22 11:51:06 +0000 |
| commit | 98eba923346615a9b2896b5a1f2377def1b73c35 (patch) | |
| tree | 69730ec106ea10b931f438e19bd2134511d4c5b7 | |
| parent | 8afb08e5b5536a76bf359c0a75ffc1738d2ad1dc (diff) | |
| download | llvm-98eba923346615a9b2896b5a1f2377def1b73c35.tar.gz llvm-98eba923346615a9b2896b5a1f2377def1b73c35.tar.bz2 llvm-98eba923346615a9b2896b5a1f2377def1b73c35.tar.xz | |
[mips] Change lwl and lwr in inlineasm_constraint.ll to lw
Summary:
lwl and lwr are not available in MIPS32r6/MIPS64r6. The purpose of the test
is to check that the '$1' expands to '0($x)' rather than to test something related
to the lwl or lwr instructions so we can simply switch to lw.
Depends on D3842
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209423 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/CodeGen/Mips/inlineasm_constraint.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll index 8701bf43fd..76b73dc276 100644 --- a/test/CodeGen/Mips/inlineasm_constraint.ll +++ b/test/CodeGen/Mips/inlineasm_constraint.ll @@ -54,10 +54,10 @@ entry: ; Now R Which takes the address of c %c = alloca i32, align 4 store i32 -4469539, i32* %c, align 4 - %8 = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1 + %8 = call i32 asm sideeffect "lw $0, 1 + $1\0A\09lw $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1 ; CHECK: #APP -; CHECK: lwl ${{[0-9]+}}, 1 + 0(${{[0-9]+}}) -; CHECK: lwr ${{[0-9]+}}, 2 + 0(${{[0-9]+}}) +; CHECK: lw ${{[0-9]+}}, 1 + 0(${{[0-9]+}}) +; CHECK: lw ${{[0-9]+}}, 2 + 0(${{[0-9]+}}) ; CHECK: #NO_APP ret i32 0 |