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authorEric Christopher <echristo@gmail.com>2013-10-14 21:52:26 +0000
committerEric Christopher <echristo@gmail.com>2013-10-14 21:52:26 +0000
commit9d0e94c16e862475dadd3dd81e1386beaf633fc1 (patch)
tree15ec827dd5c66020c07de05950c115a529ee470a
parent739eb9d82da66caa2462c90b1bf01170c25d447a (diff)
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Revert part of a fix from 2010, changes since then:
a) x86-64 TLS has been documented b) the code path should use movq for the correct relocation to be generated. I've also added a fixme for the test case that we should improve the code generated, it should look something like is documented in the tls abi document. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192631 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86InstrCompiler.td2
-rw-r--r--test/CodeGen/X86/x86-64-tls-1.ll6
2 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index f62d68ce29..9e1cdc9057 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -969,7 +969,7 @@ def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
// tls has some funny stuff here...
// This corresponds to movabs $foo@tpoff, %rax
def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
- (MOV64ri tglobaltlsaddr :$dst)>;
+ (MOV64ri32 tglobaltlsaddr :$dst)>;
// This corresponds to add $foo@tpoff, %rax
def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
(ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
diff --git a/test/CodeGen/X86/x86-64-tls-1.ll b/test/CodeGen/X86/x86-64-tls-1.ll
index 8d3b300da3..fee712d30b 100644
--- a/test/CodeGen/X86/x86-64-tls-1.ll
+++ b/test/CodeGen/X86/x86-64-tls-1.ll
@@ -1,6 +1,10 @@
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
@tm_nest_level = internal thread_local global i32 0
define i64 @z() nounwind {
-; CHECK: movabsq $tm_nest_level@TPOFF, %rcx
+; FIXME: The codegen here is primative at best and could be much better.
+; The add and the moves can be folded together.
+; CHECK: movq $tm_nest_level@TPOFF, %rcx
+; CHECK: movq %fs:0, %rax
+; CHECK: addl %ecx, %eax
ret i64 and (i64 ptrtoint (i32* @tm_nest_level to i64), i64 100)
}