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| author | Evan Cheng <evan.cheng@apple.com> | 2010-06-02 01:08:27 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-06-02 01:08:27 +0000 |
| commit | 9d709a8edb696e89b33cd3c2886c8db735b02318 (patch) | |
| tree | e3ca2e1172abd7fb5437256268bc7a7573df2439 | |
| parent | 22237771d813a2d7282fa1cdc411c2a09a71a81c (diff) | |
| download | llvm-9d709a8edb696e89b33cd3c2886c8db735b02318.tar.gz llvm-9d709a8edb696e89b33cd3c2886c8db735b02318.tar.bz2 llvm-9d709a8edb696e89b33cd3c2886c8db735b02318.tar.xz | |
Enable machine cse of instructions which define physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/MachineCSE.cpp | 5 | ||||
| -rw-r--r-- | test/CodeGen/ARM/machine-cse-cmp.ll | 18 |
2 files changed, 19 insertions, 4 deletions
diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index 6f4f7a8834..d8e2ec64da 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -31,9 +31,6 @@ using namespace llvm; STATISTIC(NumCoalesces, "Number of copies coalesced"); STATISTIC(NumCSEs, "Number of common subexpression eliminated"); -static cl::opt<bool> CSEPhysDef("machine-cse-phys-defs", - cl::init(false), cl::Hidden); - namespace { class MachineCSE : public MachineFunctionPass { const TargetInstrInfo *TII; @@ -376,7 +373,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) { // ... Unless the CS is local and it also defines the physical register // which is not clobbered in between. - if (PhysDef && CSEPhysDef) { + if (PhysDef) { unsigned CSVN = VNT.lookup(MI); MachineInstr *CSMI = Exps[CSVN]; if (PhysRegDefReaches(CSMI, MI, PhysDef)) diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll new file mode 100644 index 0000000000..c77402f3bc --- /dev/null +++ b/test/CodeGen/ARM/machine-cse-cmp.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=arm | FileCheck %s +;rdar://8003725 + +@G1 = external global i32 +@G2 = external global i32 + +define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) { +entry: +; CHECK: cmp +; CHECK: moveq +; CHECK-NOT: cmp +; CHECK: moveq + %tmp1 = icmp eq i32 %cond1, 0 + %tmp2 = select i1 %tmp1, i32 %x1, i32 %x2 + %tmp3 = select i1 %tmp1, i32 %x2, i32 %x3 + %tmp4 = add i32 %tmp2, %tmp3 + ret i32 %tmp4 +} |