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authorDaniel Sanders <daniel.sanders@imgtec.com>2013-11-22 15:47:18 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2013-11-22 15:47:18 +0000
commita24e7f7d8cc7f1e4e1582cb2f3ef9748d92fd7e4 (patch)
tree91a429c59b071fd35fcd8f7dd3185d926dd7d17d
parent21a47246f9bc122c24f799eb105aff0ae9c31ce1 (diff)
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[mips][msa] Add test case that should have been added in r195456.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195469 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll31
1 files changed, 31 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll b/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
new file mode 100644
index 0000000000..38113143e6
--- /dev/null
+++ b/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=mips < %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
+; RUN: llc -march=mipsel < %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
+
+; This test originally failed for MSA with a "Cannot select ..." error.
+; This was because undef's are ignored when checking if a vector constant is a
+; splat, but are legalized to zero if left in the DAG which changes the constant
+; into a non-splat.
+;
+; It should at least successfully build.
+
+define void @autogen_SD2090927243() {
+BB:
+ br label %CF77
+
+CF77: ; preds = %CF77, %CF80
+ %Shuff27 = shufflevector <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>,
+ <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>,
+ <16 x i32> <i32 27, i32 29, i32 31, i32 1, i32 3, i32 5, i32 undef, i32 9, i32 11, i32 13, i32 undef, i32 17, i32 19, i32 21, i32 23, i32 undef>
+ %ZE30 = zext <16 x i8> %Shuff27 to <16 x i32>
+ %Cmp32 = fcmp ueq float undef, 0x3CDA6E5E40000000
+ br i1 %Cmp32, label %CF77, label %CF
+
+CF: ; preds = %CF, %CF81
+ %E48 = extractelement <16 x i32> %ZE30, i32 14
+ br i1 undef, label %CF, label %CF78
+
+CF78: ; preds = %CF
+ ret void
+}