diff options
| author | Akira Hatanaka <ahatanak@gmail.com> | 2011-07-19 03:14:58 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-07-19 03:14:58 +0000 |
| commit | a308c670b44f068a660309d6daff7b35d531ddc4 (patch) | |
| tree | 8369161141b0ac70d8783240c376c8c41894199f | |
| parent | 9710f06d668bd790a2a18a6c2cd65b35414d66ab (diff) | |
| download | llvm-a308c670b44f068a660309d6daff7b35d531ddc4.tar.gz llvm-a308c670b44f068a660309d6daff7b35d531ddc4.tar.bz2 llvm-a308c670b44f068a660309d6daff7b35d531ddc4.tar.xz | |
Do not insert instructions in reverse order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135464 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 0dd8b06557..d604a65a68 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -917,15 +917,16 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, // sra dest,tmp12,24 BB = exitMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - // reverse order - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) - .addReg(Tmp12).addImm(ShiftImm); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp12) - .addReg(Tmp11).addImm(ShiftImm); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp11) - .addReg(Tmp10).addReg(Shift); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::AND), Tmp10) + + MachineBasicBlock::iterator II = BB->begin(); + BuildMI(*BB, II, dl, TII->get(Mips::AND), Tmp10) .addReg(Oldval).addReg(Mask); + BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp11) + .addReg(Tmp10).addReg(Shift); + BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp12) + .addReg(Tmp11).addImm(ShiftImm); + BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest) + .addReg(Tmp12).addImm(ShiftImm); MI->eraseFromParent(); // The instruction is gone now. @@ -1114,13 +1115,14 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, // sra dest,tmp9,24 BB = exitMBB; int64_t ShiftImm = (Size == 1) ? 24 : 16; - // reverse order - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) - .addReg(Tmp9).addImm(ShiftImm); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp9) - .addReg(Tmp8).addImm(ShiftImm); - BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp8) + + MachineBasicBlock::iterator II = BB->begin(); + BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp8) .addReg(Oldval4).addReg(Shift); + BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp9) + .addReg(Tmp8).addImm(ShiftImm); + BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest) + .addReg(Tmp9).addImm(ShiftImm); MI->eraseFromParent(); // The instruction is gone now. |