Clean up predicates on ARM target instruction aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 61 insertions, 61 deletions

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 0f4b2648cf..eba55944d2 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -219,9 +219,20 @@ def shr_imm64 : Operand<i32> {
 }
 
 //===----------------------------------------------------------------------===//
+// ARM Assembler alias templates.
+//
+class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
+      : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
+class  tInstAlias<string Asm, dag Result, bit Emit = 0b1>
+      : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
+class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
+      : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
+
+//===----------------------------------------------------------------------===//
 // ARM Instruction templates.
 //
 
+
 class InstTemplate<AddrMode am, int sz, IndexMode im,
                    Format f, Domain d, string cstr, InstrItinClass itin>
   : Instruction {
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 24303fc9b3..b1c80d4c62 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -4751,75 +4751,71 @@ def : MnemonicAlias<"stmea", "stm">;
 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
 // shift amount is zero (i.e., unspecified).
 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
-                (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
+                (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
+        Requires<[IsARM, HasV6]>;
 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
-                (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
+                (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
+        Requires<[IsARM, HasV6]>;
 
 // PUSH/POP aliases for STM/LDM
-def : InstAlias<"push${p} $regs",
-                (STMDB_UPD SP, pred:$p, reglist:$regs)>;
-def : InstAlias<"pop${p} $regs",
-                (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
+def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
+def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
 
 // RSB two-operand forms (optional explicit destination operand)
-def : InstAlias<"rsb${s}${p} $Rdn, $imm",
-                (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
-         Requires<[IsARM]>;
-def : InstAlias<"rsb${s}${p} $Rdn, $Rm",
-                (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
-         Requires<[IsARM]>;
-def : InstAlias<"rsb${s}${p} $Rdn, $shift",
+def : ARMInstAlias<"rsb${s}${p} $Rdn, $imm",
+                (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"rsb${s}${p} $Rdn, $Rm",
+                (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift",
                 (RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
-                        cc_out:$s)>, Requires<[IsARM]>;
-def : InstAlias<"rsb${s}${p} $Rdn, $shift",
+                        cc_out:$s)>;
+def : ARMInstAlias<"rsb${s}${p} $Rdn, $shift",
                 (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
-                        cc_out:$s)>, Requires<[IsARM]>;
+                        cc_out:$s)>;
 // RSC two-operand forms (optional explicit destination operand)
-def : InstAlias<"rsc${s}${p} $Rdn, $imm",
-                (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
-         Requires<[IsARM]>;
-def : InstAlias<"rsc${s}${p} $Rdn, $Rm",
-                (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
-         Requires<[IsARM]>;
-def : InstAlias<"rsc${s}${p} $Rdn, $shift",
+def : ARMInstAlias<"rsc${s}${p} $Rdn, $imm",
+                (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"rsc${s}${p} $Rdn, $Rm",
+                (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift",
                 (RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
-                        cc_out:$s)>, Requires<[IsARM]>;
-def : InstAlias<"rsc${s}${p} $Rdn, $shift",
+                        cc_out:$s)>;
+def : ARMInstAlias<"rsc${s}${p} $Rdn, $shift",
                 (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
-                        cc_out:$s)>, Requires<[IsARM]>;
+                        cc_out:$s)>;
 
 // SSAT/USAT optional shift operand.
-def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
+def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
                 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
-def : InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
+def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
                 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
 
 
 // Extend instruction optional rotate operand.
-def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
+def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
                 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
+def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
                 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
+def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
                 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"sxtb${p} $Rd, $Rm",
+def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
                 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"sxtb16${p} $Rd, $Rm",
+def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
                 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"sxth${p} $Rd, $Rm",
+def : ARMInstAlias<"sxth${p} $Rd, $Rm",
                 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
 
-def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
+def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
                 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
+def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
                 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
+def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
                 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"uxtb${p} $Rd, $Rm",
+def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
                 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"uxtb16${p} $Rd, $Rm",
+def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
                 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
-def : InstAlias<"uxth${p} $Rd, $Rm",
+def : ARMInstAlias<"uxth${p} $Rd, $Rm",
                 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
 
 
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index a151c0dfaa..f58cb34e60 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -1017,9 +1017,8 @@ def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
 }
 // Because we have an explicit tMOVSr below, we need an alias to handle
 // the immediate "movs" form here. Blech.
-def : InstAlias <"movs $Rdn, $imm",
-                 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>,
-        Requires<[IsThumb]>;
+def : tInstAlias <"movs $Rdn, $imm",
+                 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
 
 // A7-73: MOV(2) - mov setting flag.
 
@@ -1061,9 +1060,8 @@ def tMUL :                      // A8.6.105 T1
   let AsmMatchConverter = "cvtThumbMultiply";
 }
 
-def : InstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
-                                               pred:$p)>,
-          Requires<[IsThumb]>;
+def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
+                                               pred:$p)>;
 
 // Move inverse register
 def tMVN :                      // A8.6.107
@@ -1115,9 +1113,8 @@ def tRSB :                      // A8.6.141
                "rsb", "\t$Rd, $Rn, #0",
                [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
 
-def : InstAlias<"neg${s}${p} $Rd, $Rm",
-                (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>,
-        Requires<[IsThumb]>;
+def : tInstAlias<"neg${s}${p} $Rd, $Rm",
+                 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
 
 // Subtract with carry register
 let Uses = [CPSR] in
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index fbe80c2f24..ec73b35fe5 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -504,21 +504,18 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
    }
   // Assembly aliases for optional destination operand when it's the same
   // as the source operand.
-  def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
+  def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
      (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
                                                     t2_so_imm:$imm, pred:$p,
-                                                    cc_out:$s)>,
-     Requires<[IsThumb2]>;
-  def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
+                                                    cc_out:$s)>;
+  def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
      (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
                                                     rGPR:$Rm, pred:$p,
-                                                    cc_out:$s)>,
-     Requires<[IsThumb2]>;
-  def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
+                                                    cc_out:$s)>;
+  def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
      (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
                                                     t2_so_reg:$shift, pred:$p,
-                                                    cc_out:$s)>,
-     Requires<[IsThumb2]>;
+                                                    cc_out:$s)>;
 }
 
 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
@@ -1557,9 +1554,8 @@ def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
   let Inst{15} = 0;
 }
 
-def : InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
-                                                 pred:$p, cc_out:$s)>,
-                Requires<[IsThumb2]>;
+def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
+                                                   pred:$p, cc_out:$s)>;
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,