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| author | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-13 20:13:58 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-13 20:13:58 +0000 |
| commit | a4b97f327de0332ef1e68bb3c3b94fed0ffe3520 (patch) | |
| tree | 4bd6530f2f276dfecc880ba77c548c1ad7502890 | |
| parent | 8f28aaf72c61a493dfcd1b838ff8c5050352b5cd (diff) | |
| download | llvm-a4b97f327de0332ef1e68bb3c3b94fed0ffe3520.tar.gz llvm-a4b97f327de0332ef1e68bb3c3b94fed0ffe3520.tar.bz2 llvm-a4b97f327de0332ef1e68bb3c3b94fed0ffe3520.tar.xz | |
Add pattern used to match MipsLo, which is needed when the instruction selector
tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139634 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 5 | ||||
| -rw-r--r-- | test/CodeGen/Mips/mipslopat.ll | 19 |
2 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index ccf23076f0..d4c624fe04 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -734,16 +734,20 @@ def : Pat<(MipsJmpLink (i32 texternalsym:$dst)), // hi/lo relocs def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; +def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; +def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), (ADDiu CPURegs:$hi, tblockaddress:$lo)>; def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; +def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), (ADDiu CPURegs:$hi, tjumptable:$lo)>; def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; +def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), (ADDiu CPURegs:$hi, tconstpool:$lo)>; @@ -759,6 +763,7 @@ def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)), // tprel hi/lo def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; +def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)), (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; diff --git a/test/CodeGen/Mips/mipslopat.ll b/test/CodeGen/Mips/mipslopat.ll new file mode 100644 index 0000000000..02798285b4 --- /dev/null +++ b/test/CodeGen/Mips/mipslopat.ll @@ -0,0 +1,19 @@ +; This test does not check the machine code output. +; RUN: llc -march=mips < %s + +@stat_vol_ptr_int = internal global i32* null, align 4 +@stat_ptr_vol_int = internal global i32* null, align 4 + +define void @simple_vol_file() nounwind { +entry: + %tmp = volatile load i32** @stat_vol_ptr_int, align 4 + %0 = bitcast i32* %tmp to i8* + call void @llvm.prefetch(i8* %0, i32 0, i32 0, i32 1) + %tmp1 = load i32** @stat_ptr_vol_int, align 4 + %1 = bitcast i32* %tmp1 to i8* + call void @llvm.prefetch(i8* %1, i32 0, i32 0, i32 1) + ret void +} + +declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind + |