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authorChad Rosier <mcrosier@apple.com>2011-11-04 23:09:49 +0000
committerChad Rosier <mcrosier@apple.com>2011-11-04 23:09:49 +0000
commita4e07270bccb3cb6774af975300628e072bf03f1 (patch)
treed75fe8ff05cd3c61aeaae9e4e3d5469dc79da1fe
parenta54c8ea8cfcba3682afb53301b93ecc59fc9897a (diff)
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When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8, i16) we should not sign-extend. This prevents us from materializing things such as 'true' (i.e., i1 1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143743 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMFastISel.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index e8e8124b66..a315c305fc 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -551,7 +551,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
// If we can do this in a single instruction without a constant pool entry
// do so now.
const ConstantInt *CI = cast<ConstantInt>(C);
- if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
+ if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
unsigned ImmReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,