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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-06-01 22:39:25 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-06-01 22:39:25 +0000 |
commit | a5135f60dd95275dcbc1123f866889151ced933d (patch) | |
tree | 5e0dc69e54f439ac7bb172b3d378844eed75e103 | |
parent | 23d3d4595c23784494cba422a76428e48431413a (diff) | |
download | llvm-a5135f60dd95275dcbc1123f866889151ced933d.tar.gz llvm-a5135f60dd95275dcbc1123f866889151ced933d.tar.bz2 llvm-a5135f60dd95275dcbc1123f866889151ced933d.tar.xz |
Properly compose subregister indices when coalescing.
The comment about ordering of subreg indices is no longer true.
This exposed a bug in the new substVirtReg method that is also fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105294 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 3 | ||||
-rw-r--r-- | lib/CodeGen/SimpleRegisterCoalescing.cpp | 14 |
2 files changed, 3 insertions, 14 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index ce0c5e6a87..402178dc6d 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -117,7 +117,8 @@ void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, if (SubIdx && getSubReg()) SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); setReg(Reg); - setSubReg(SubIdx); + if (SubIdx) + setSubReg(SubIdx); } void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index ed3c243ff3..7c1bc47fa9 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -848,19 +848,7 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, continue; } - // Sub-register indexes goes from small to large. e.g. - // RAX: 1 -> AL, 2 -> AX, 3 -> EAX - // EAX: 1 -> AL, 2 -> AX - // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose - // sub-register 2 is also AX. - // - // FIXME: Properly compose subreg indices for all targets. - // - if (SubIdx && OldSubIdx && SubIdx != OldSubIdx) - ; - else if (SubIdx) - O.setSubReg(SubIdx); - O.setReg(DstReg); + O.substVirtReg(DstReg, SubIdx, *tri_); DEBUG({ dbgs() << "\t\tupdated: "; |