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| author | Dale Johannesen <dalej@apple.com> | 2008-09-02 20:30:23 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2008-09-02 20:30:23 +0000 |
| commit | a619d012c13bee0572b96b045723dff5a117a5c2 (patch) | |
| tree | 8ae1b2c7dc05f31f9caf5f4223353bf8e5861109 | |
| parent | d2ff647964ed242e67ac12f7d21a58c864309d95 (diff) | |
| download | llvm-a619d012c13bee0572b96b045723dff5a117a5c2.tar.gz llvm-a619d012c13bee0572b96b045723dff5a117a5c2.tar.bz2 llvm-a619d012c13bee0572b96b045723dff5a117a5c2.tar.xz | |
Fix some bugs in the code sequences for atomics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55643 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 5aaded5819..3fb4263b0c 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3881,8 +3881,8 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, MachineRegisterInfo &RegInfo = F->getRegInfo(); unsigned TmpReg = (!BinOpcode) ? incr : RegInfo.createVirtualRegister( - is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass : - (const TargetRegisterClass *) &PPC::G8RCRegClass); + is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : + (const TargetRegisterClass *) &PPC::GPRCRegClass); // thisMBB: // ... @@ -3944,8 +3944,8 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, MachineRegisterInfo &RegInfo = F->getRegInfo(); const TargetRegisterClass *RC = - is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass : - (const TargetRegisterClass *) &PPC::G8RCRegClass; + is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : + (const TargetRegisterClass *) &PPC::GPRCRegClass; unsigned PtrReg = RegInfo.createVirtualRegister(RC); unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); unsigned ShiftReg = RegInfo.createVirtualRegister(RC); @@ -3969,7 +3969,7 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, // anywhere in the word. Hence all this nasty bookkeeping code. // add ptr1, ptrA, ptrB [copy if ptrA==0] // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] - // xor shift, shift1, 24 [16] + // xori shift, shift1, 24 [16] // rlwinm ptr, ptr1, 0, 0, 29 // slw incr2, incr, shift // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] @@ -3994,7 +3994,7 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, } BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); - BuildMI(BB, TII->get(is64bit ? PPC::XOR8 : PPC::XOR), ShiftReg) + BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); if (is64bit) BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) @@ -4251,8 +4251,8 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineRegisterInfo &RegInfo = F->getRegInfo(); const TargetRegisterClass *RC = - is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass : - (const TargetRegisterClass *) &PPC::G8RCRegClass; + is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : + (const TargetRegisterClass *) &PPC::GPRCRegClass; unsigned PtrReg = RegInfo.createVirtualRegister(RC); unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); unsigned ShiftReg = RegInfo.createVirtualRegister(RC); @@ -4277,7 +4277,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // anywhere in the word. Hence all this nasty bookkeeping code. // add ptr1, ptrA, ptrB [copy if ptrA==0] // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] - // xor shift, shift1, 24 [16] + // xori shift, shift1, 24 [16] // rlwinm ptr, ptr1, 0, 0, 29 // slw newval2, newval, shift // slw oldval2, oldval,shift @@ -4309,7 +4309,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, } BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); - BuildMI(BB, TII->get(is64bit ? PPC::XOR8 : PPC::XOR), ShiftReg) + BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); if (is64bit) BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) |