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| author | Bob Wilson <bob.wilson@apple.com> | 2011-10-18 17:34:51 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2011-10-18 17:34:51 +0000 |
| commit | ad952ad8f05a1c5082a6b7ac8627008fa24d722a (patch) | |
| tree | cbb3b398bd2102a32f4110b0d9e655d55385f17f | |
| parent | db2b18febaea04d01b3dcb24fc44d5be7bd27a00 (diff) | |
| download | llvm-ad952ad8f05a1c5082a6b7ac8627008fa24d722a.tar.gz llvm-ad952ad8f05a1c5082a6b7ac8627008fa24d722a.tar.bz2 llvm-ad952ad8f05a1c5082a6b7ac8627008fa24d722a.tar.xz | |
Fix incorrect check for sign-extended constant BUILD_VECTOR.
<rdar://problem/10298332>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142371 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vmul.ll | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 1615f5b140..7753006774 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -4527,7 +4527,7 @@ static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, unsigned HalfSize = EltSize / 2; if (isSigned) { int64_t SExtVal = C->getSExtValue(); - if ((SExtVal >> HalfSize) != (SExtVal >> EltSize)) + if (SExtVal != SExtVal << (64 - HalfSize) >> (64 - HalfSize)) return false; } else { if ((C->getZExtValue() >> HalfSize) != 0) diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index 1780d6e66b..61d89bbae8 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -514,3 +514,14 @@ entry: store <8 x i8> %10, <8 x i8>* %11, align 8 ret void } + +; If one operand has a zero-extend and the other a sign-extend, vmull +; cannot be used. +define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) { +; CHECK: vmullWithInconsistentExtensions +; CHECK-NOT: vmull.s8 + %1 = sext <8 x i8> %vec to <8 x i16> + %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> + %3 = extractelement <8 x i16> %2, i32 0 + ret i16 %3 +} |