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author | Craig Topper <craig.topper@gmail.com> | 2012-11-27 08:14:24 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2012-11-27 08:14:24 +0000 |
commit | af87dae12cab8d2e5cab033a5ab60af98e1837fe (patch) | |
tree | d8be4f5a35feb7d8b0b65e882920076d6f5304c6 | |
parent | 1c689f7a40f37dc308471dcd65e6a4d43716b073 (diff) | |
download | llvm-af87dae12cab8d2e5cab033a5ab60af98e1837fe.tar.gz llvm-af87dae12cab8d2e5cab033a5ab60af98e1837fe.tar.bz2 llvm-af87dae12cab8d2e5cab033a5ab60af98e1837fe.tar.xz |
Make PrintReg constructor explicit to prevent weird implicit conversions from accidentally being triggered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168686 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/Target/TargetRegisterInfo.h | 3 | ||||
-rw-r--r-- | test/CodeGen/X86/sse2-blend.ll | 42 |
2 files changed, 2 insertions, 43 deletions
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index afa2ee2744..2445897841 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -876,7 +876,8 @@ class PrintReg { unsigned Reg; unsigned SubIdx; public: - PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) + explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, + unsigned subidx = 0) : TRI(tri), Reg(reg), SubIdx(subidx) {} void print(raw_ostream&) const; }; diff --git a/test/CodeGen/X86/sse2-blend.ll b/test/CodeGen/X86/sse2-blend.ll index 2f4317bf29..f08209f75b 100644 --- a/test/CodeGen/X86/sse2-blend.ll +++ b/test/CodeGen/X86/sse2-blend.ll @@ -1,47 +1,5 @@ ; RUN: llc < %s -march=x86 -mcpu=yonah -mattr=+sse2,-sse41 | FileCheck %s -; CHECK: vsel_float -; CHECK: pandn -; CHECK: pand -; CHECK: por -; CHECK: ret -define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) { - %A = load <4 x float>* %v1 - %B = load <4 x float>* %v2 - %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %A, <4 x float> %B - store <4 x float > %vsel, <4 x float>* %v1 - ret void -} - -; CHECK: vsel_i32 -; CHECK: pandn -; CHECK: pand -; CHECK: por -; CHECK: ret -define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) { - %A = load <4 x i32>* %v1 - %B = load <4 x i32>* %v2 - %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B - store <4 x i32 > %vsel, <4 x i32>* %v1 - ret void -} - -; Without forcing instructions, fall back to the preferred PS domain. -; CHECK: vsel_i64 -; CHECK: xorps -; CHECK: andps -; CHECK: andnps -; CHECK: orps -; CHECK: ret - -define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) { - %A = load <4 x i64>* %v1 - %B = load <4 x i64>* %v2 - %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %A, <4 x i64> %B - store <4 x i64 > %vsel, <4 x i64>* %v1 - ret void -} - ; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_double ; CHECK: xorps |