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author | Akira Hatanaka <ahatanaka@apple.com> | 2014-03-28 23:28:07 +0000 |
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committer | Akira Hatanaka <ahatanaka@apple.com> | 2014-03-28 23:28:07 +0000 |
commit | b3cb36026abd673d8ee13105647b678c3ba88b0e (patch) | |
tree | e00e6cffd9068246482aa3a4dee0f76319bc6445 | |
parent | 1fc0d63775bb93ed295506c4c563b02256fbd6bd (diff) | |
download | llvm-b3cb36026abd673d8ee13105647b678c3ba88b0e.tar.gz llvm-b3cb36026abd673d8ee13105647b678c3ba88b0e.tar.bz2 llvm-b3cb36026abd673d8ee13105647b678c3ba88b0e.tar.xz |
[x86] Fix printing of register operands with q modifier.
Emit 32-bit register names instead of 64-bit register names if the target does
not have 64-bit general purpose registers.
<rdar://problem/14653996>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205067 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86AsmPrinter.cpp | 8 | ||||
-rw-r--r-- | test/CodeGen/X86/inline-asm-modifier-q.ll | 12 |
2 files changed, 17 insertions, 3 deletions
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp index 03cf5555cd..0ded0864ab 100644 --- a/lib/Target/X86/X86AsmPrinter.cpp +++ b/lib/Target/X86/X86AsmPrinter.cpp @@ -363,9 +363,11 @@ static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO, case 'k': // Print SImode register Reg = getX86SubSuperRegister(Reg, MVT::i32); break; - case 'q': // Print DImode register - // FIXME: gcc will actually print e instead of r for 32-bit. - Reg = getX86SubSuperRegister(Reg, MVT::i64); + case 'q': + // Print 64-bit register names if 64-bit integer registers are available. + // Otherwise, print 32-bit register names. + MVT::SimpleValueType Ty = P.getSubtarget().is64Bit() ? MVT::i64 : MVT::i32; + Reg = getX86SubSuperRegister(Reg, Ty); break; } diff --git a/test/CodeGen/X86/inline-asm-modifier-q.ll b/test/CodeGen/X86/inline-asm-modifier-q.ll new file mode 100644 index 0000000000..8063d48a2c --- /dev/null +++ b/test/CodeGen/X86/inline-asm-modifier-q.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=x86 -no-integrated-as | FileCheck %s + +; If the target does not have 64-bit integer registers, emit 32-bit register +; names. + +; CHECK: movq (%e{{[abcd]}}x, %ebx, 4) + +define void @q_modifier(i32* %p) { +entry: + tail call void asm sideeffect "movq (${0:q}, %ebx, 4), %mm0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %p) + ret void +} |