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| author | Bob Wilson <bob.wilson@apple.com> | 2009-10-22 16:52:21 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-10-22 16:52:21 +0000 |
| commit | bac6ed4ba4b5b912470e3c48f86c3e74a2f36d7b (patch) | |
| tree | 00e0395dd031f2fe6dd3b2d262c63a9e1c8873be | |
| parent | 09b5d90429258f92f5e5ac98411a71460bcd9230 (diff) | |
| download | llvm-bac6ed4ba4b5b912470e3c48f86c3e74a2f36d7b.tar.gz llvm-bac6ed4ba4b5b912470e3c48f86c3e74a2f36d7b.tar.bz2 llvm-bac6ed4ba4b5b912470e3c48f86c3e74a2f36d7b.tar.xz | |
Revert 84843. Evan, this was breaking some of the if-conversion tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMTargetMachine.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/ARM/ifcvt5.ll | 3 |
2 files changed, 6 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index bd2e7347d4..c1da6ce88b 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -103,16 +103,18 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) { + if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) PM.add(createARMLoadStoreOptimizationPass()); - PM.add(createIfConverterPass()); - } return true; } bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { + // FIXME: temporarily disabling load / store optimization pass for Thumb1. + if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) + PM.add(createIfConverterPass()); + if (Subtarget.isThumb2()) { PM.add(createThumb2ITBlockPass()); PM.add(createThumb2SizeReductionPass()); diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index 92bbe75baa..e9145ac36d 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -11,8 +11,7 @@ entry: define void @t1(i32 %a, i32 %b) { ; CHECK: t1: -; CHECK: movge -; CHECK: blge _foo +; CHECK: ldmltfd sp!, {r7, pc} entry: %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock |