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authorZhongxing Xu <xuzhongxing@gmail.com>2010-05-17 09:47:55 +0000
committerZhongxing Xu <xuzhongxing@gmail.com>2010-05-17 09:47:55 +0000
commitbae5210321e0c3ea28723334841555135a61e915 (patch)
treec17a07d3e911b3573f9f9ccb3cdb86b9bab48a66
parent0c9e4f5f3ff139733d74462a0ad5b94014e764a8 (diff)
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Remove unused member variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103936 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/CodeGen/ScheduleDAG.h2
-rw-r--r--lib/CodeGen/ScheduleDAG.cpp1
2 files changed, 0 insertions, 3 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 7c025e3acb..67af16545a 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -34,7 +34,6 @@ namespace llvm {
class SDNode;
class TargetInstrInfo;
class TargetInstrDesc;
- class TargetLowering;
class TargetMachine;
class TargetRegisterClass;
template<class Graph> class GraphWriter;
@@ -456,7 +455,6 @@ namespace llvm {
const TargetMachine &TM; // Target processor
const TargetInstrInfo *TII; // Target instruction information
const TargetRegisterInfo *TRI; // Target processor register info
- const TargetLowering *TLI; // Target lowering info
MachineFunction &MF; // Machine function
MachineRegisterInfo &MRI; // Virtual/real register map
std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
diff --git a/lib/CodeGen/ScheduleDAG.cpp b/lib/CodeGen/ScheduleDAG.cpp
index 587f001cc7..da20c12c36 100644
--- a/lib/CodeGen/ScheduleDAG.cpp
+++ b/lib/CodeGen/ScheduleDAG.cpp
@@ -27,7 +27,6 @@ ScheduleDAG::ScheduleDAG(MachineFunction &mf)
: TM(mf.getTarget()),
TII(TM.getInstrInfo()),
TRI(TM.getRegisterInfo()),
- TLI(TM.getTargetLowering()),
MF(mf), MRI(mf.getRegInfo()),
EntrySU(), ExitSU() {
}