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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-05-10 02:09:24 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-05-10 02:09:24 +0000 |
| commit | bdd9b1e89f22d11d38012bfec8101b063efb4549 (patch) | |
| tree | 80a9fe995828fae4b51b5bd8479daad707f62773 | |
| parent | a70d02ff2841d535875fe80bd3d3c25ba90613da (diff) | |
| download | llvm-bdd9b1e89f22d11d38012bfec8101b063efb4549.tar.gz llvm-bdd9b1e89f22d11d38012bfec8101b063efb4549.tar.bz2 llvm-bdd9b1e89f22d11d38012bfec8101b063efb4549.tar.xz | |
R600: Expand vselect for v4i32 and v2i32
v2: Add vselect v4i32 test
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181576 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/R600/vselect.ll | 17 |
2 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index c6e2136ff4..6dec4d1dbe 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -78,6 +78,9 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setOperationAction(ISD::SELECT, MVT::i32, Custom); setOperationAction(ISD::SELECT, MVT::f32, Custom); + setOperationAction(ISD::VSELECT, MVT::v4i32, Expand); + setOperationAction(ISD::VSELECT, MVT::v2i32, Expand); + // Legalize loads and stores to the private address space. setOperationAction(ISD::LOAD, MVT::i32, Custom); setOperationAction(ISD::LOAD, MVT::v2i32, Custom); diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll new file mode 100644 index 0000000000..6e459df847 --- /dev/null +++ b/test/CodeGen/R600/vselect.ll @@ -0,0 +1,17 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @test_select_v4i32 +; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { +entry: + %0 = load <4 x i32> addrspace(1)* %in0 + %1 = load <4 x i32> addrspace(1)* %in1 + %cmp = icmp ne <4 x i32> %0, %1 + %result = select <4 x i1> %cmp, <4 x i32> %0, <4 x i32> %1 + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} |