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authorChris Lattner <sabre@nondot.org>2006-02-28 07:08:22 +0000
committerChris Lattner <sabre@nondot.org>2006-02-28 07:08:22 +0000
commitbf751e2d6f3779b78c9a00fb9887e1b25faa880c (patch)
treedb05c3f69920cfad18ab01f41873338de00c6496
parentc7d855ea2e3ab66faa8006071e9b18934fd9ab30 (diff)
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Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
but I don't know what other PPC impls do. If someone could update the proc table, I would appreciate it :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPC.td6
-rw-r--r--lib/Target/PowerPC/PPCSubtarget.h2
2 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index 8b9e3a7ac1..272f6d6a16 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -29,6 +29,8 @@ def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
"Enable GPUL instructions">;
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
"Enable the fsqrt instruction">;
+def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
+ "Enable the stfiwx instruction">;
//===----------------------------------------------------------------------===//
// Register File Description
@@ -58,10 +60,10 @@ def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"750", G3Itineraries, []>;
def : Processor<"970", G5Itineraries,
- [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+ [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;
def : Processor<"g5", G5Itineraries,
- [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+ [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;
diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h
index 3f1454ce52..4f838741ad 100644
--- a/lib/Target/PowerPC/PPCSubtarget.h
+++ b/lib/Target/PowerPC/PPCSubtarget.h
@@ -37,6 +37,7 @@ protected:
bool Has64BitRegs;
bool HasAltivec;
bool HasFSQRT;
+ bool HasSTFIWX;
bool IsAIX;
bool IsDarwin;
public:
@@ -60,6 +61,7 @@ public:
bool hasFSQRT() const { return HasFSQRT; }
+ bool hasSTFIWX() const { return HasSTFIWX; }
bool has64BitRegs() const { return Has64BitRegs; }
bool hasAltivec() const { return HasAltivec; }