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author | Alp Toker <alp@nuanti.com> | 2014-02-25 04:21:15 +0000 |
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committer | Alp Toker <alp@nuanti.com> | 2014-02-25 04:21:15 +0000 |
commit | bf930d5c1fce8103d7a047d10d1a4543f28a4dd8 (patch) | |
tree | 26755a27ad02049ce66d956d41a6c4c6600d8cda | |
parent | eb1b5ba880cbbc5aab1064c2ad0a95c8ca253de8 (diff) | |
download | llvm-bf930d5c1fce8103d7a047d10d1a4543f28a4dd8.tar.gz llvm-bf930d5c1fce8103d7a047d10d1a4543f28a4dd8.tar.bz2 llvm-bf930d5c1fce8103d7a047d10d1a4543f28a4dd8.tar.xz |
Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202107 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/RegAllocGreedy.cpp | 2 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfoV4.td | 6 | ||||
-rw-r--r-- | lib/Transforms/Scalar/ConstantHoisting.cpp | 2 | ||||
-rw-r--r-- | test/MC/COFF/section-name-encoding.s | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index 3c3f622759..21e23df107 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -1916,7 +1916,7 @@ RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, /// R3 is available. /// Recoloring => vC = R1, vA = R2, vB = R3 /// -/// \p Order defines the prefered allocation order for \p VirtReg. +/// \p Order defines the preferred allocation order for \p VirtReg. /// \p NewRegs will contain any new virtual register that have been created /// (split, spill) during the process and that must be assigned. /// \p FixedRegisters contains all the virtual registers that cannot be diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index d2600dffb0..a95fb80e5f 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -3198,7 +3198,7 @@ def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))), // i8 -> i64 loads -// We need a complexity of 120 here to overide preceeding handling of +// We need a complexity of 120 here to override preceding handling of // zextloadi8. let Predicates = [HasV4T], AddedComplexity = 120 in { def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), @@ -3220,7 +3220,7 @@ def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)), (i64 (SXTW (LDrib_abs_V4 FoldGlobalAddr:$addr)))>; } // i16 -> i64 loads -// We need a complexity of 120 here to overide preceeding handling of +// We need a complexity of 120 here to override preceding handling of // zextloadi16. let AddedComplexity = 120 in { def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), @@ -3248,7 +3248,7 @@ def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)), Requires<[HasV4T]>; } // i32->i64 loads -// We need a complexity of 120 here to overide preceeding handling of +// We need a complexity of 120 here to override preceding handling of // zextloadi32. let AddedComplexity = 120 in { def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), diff --git a/lib/Transforms/Scalar/ConstantHoisting.cpp b/lib/Transforms/Scalar/ConstantHoisting.cpp index 0fca617be7..6250620c0f 100644 --- a/lib/Transforms/Scalar/ConstantHoisting.cpp +++ b/lib/Transforms/Scalar/ConstantHoisting.cpp @@ -454,7 +454,7 @@ bool ConstantHoisting::OptimizeConstants(Function &F) { // base constant. FindBaseConstants(); - // Finaly hoist the base constant and emit materializating code for dependent + // Finally hoist the base constant and emit materializating code for dependent // constants. MadeChange |= EmitBaseConstants(F); diff --git a/test/MC/COFF/section-name-encoding.s b/test/MC/COFF/section-name-encoding.s index f8de6c3dc1..74cd490bd3 100644 --- a/test/MC/COFF/section-name-encoding.s +++ b/test/MC/COFF/section-name-encoding.s @@ -76,7 +76,7 @@ pad_sections_ex aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa // //AAmJa4 == 1000029 + 12 + (5 * (2 + (9 * 20 * 10 * 1000) + 1)) == 38*64^3 + 9*64^2 + 26*64 + 56 // v | | v ~~~~~~~~~~~~~~~~~~ v -// seven_digit offset v v "p0" pad NUL seperator +// seven_digit offset v v "p0" pad NUL separator // "seven_digit\0" # of pad sections // // "2F 2F 41 41 6D 4A 61 34" is "//AAmJa4", which decodes to "0 0 38 9 26 56". |