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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 10:02:06 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 10:02:06 +0000 |
| commit | c32a8c9073e5aafe9b4c41dddd416d378216758f (patch) | |
| tree | 97c4db56a283742c2b7dc84b4204713b6b7f4cd3 | |
| parent | 9cabfa68420fbd202f4fde214b5aa857352da0f3 (diff) | |
| download | llvm-c32a8c9073e5aafe9b4c41dddd416d378216758f.tar.gz llvm-c32a8c9073e5aafe9b4c41dddd416d378216758f.tar.bz2 llvm-c32a8c9073e5aafe9b4c41dddd416d378216758f.tar.xz | |
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
no pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/shift_ops.ll | 4 |
2 files changed, 9 insertions, 3 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 19327d8acf..08ebb9291e 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1752,9 +1752,11 @@ SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, // Both upper and lower are special, lower to a constant pool load: if (lower_special && upper_special) { - SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64); - return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, - SplatValCN, SplatValCN); + SDValue UpperVal = DAG.getConstant(upper, MVT::i32); + SDValue LowerVal = DAG.getConstant(lower, MVT::i32); + SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + UpperVal, LowerVal, UpperVal, LowerVal); + return DAG.getNode(ISD::BITCAST, dl, OpVT, BV); } SDValue LO32; diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll index 3252c776ec..8ecf15432d 100644 --- a/test/CodeGen/CellSPU/shift_ops.ll +++ b/test/CodeGen/CellSPU/shift_ops.ll @@ -342,3 +342,7 @@ define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) { %rv = ashr <8 x i16> %val, %sh ret <8 x i16> %rv } + +define <2 x i64> @special_const() { + ret <2 x i64> <i64 4294967295, i64 4294967295> +} |