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| author | Bob Wilson <bob.wilson@apple.com> | 2010-08-05 18:23:43 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-08-05 18:23:43 +0000 |
| commit | cff71788446f17fa691a2768d8c11f46ae3206a2 (patch) | |
| tree | cca754575d8fd97d964fde092f35c7eba9d4ef86 | |
| parent | a330d4c3ea4037a67e766f11d0010e681f3edf68 (diff) | |
| download | llvm-cff71788446f17fa691a2768d8c11f46ae3206a2.tar.gz llvm-cff71788446f17fa691a2768d8c11f46ae3206a2.tar.bz2 llvm-cff71788446f17fa691a2768d8c11f46ae3206a2.tar.xz | |
Add an ARM RSBrr instruction for disassembly only.
Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 10 | ||||
| -rw-r--r-- | test/MC/Disassembler/arm-tests.txt | 4 |
2 files changed, 13 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 2e78328ff0..2ca2415313 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1629,13 +1629,21 @@ defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs", defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs", BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>; -// These don't define reg/reg forms, because they are handled above. def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iALUi, "rsb", "\t$dst, $a, $b", [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> { let Inst{25} = 1; } +// The reg/reg form is only defined for the disassembler; for codegen it is +// equivalent to SUBrr. +def RSBrr : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, + IIC_iALUr, "rsb", "\t$dst, $a, $b", + [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 0; + let Inst{11-4} = 0b00000000; +} + def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iALUsr, "rsb", "\t$dst, $a, $b", [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> { diff --git a/test/MC/Disassembler/arm-tests.txt b/test/MC/Disassembler/arm-tests.txt index 45f739f114..242d5ec110 100644 --- a/test/MC/Disassembler/arm-tests.txt +++ b/test/MC/Disassembler/arm-tests.txt @@ -61,6 +61,10 @@ # CHECK: rfedb r0! 0x00 0x0a 0x30 0xf9 +# CHECK-NOT: rsbeq r0, r2, r0, lsl #0 +# CHECK: rsbeq r0, r2, r0 +0x00 0x00 0x62 0x00 + # CHECK: sbcs r0, pc, #1 0x01 0x00 0xdf 0xe2 |