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| author | Johnny Chen <johnny.chen@apple.com> | 2010-02-23 20:51:23 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2010-02-23 20:51:23 +0000 |
| commit | d7283d9c54dbc45d47ee0fbed0fbdcbf0ae74f23 (patch) | |
| tree | d508a25ad0d918b8f15981a480e4e4f8fb20bec8 | |
| parent | 81d97c04951bff899d196a095bbd3375410bed1d (diff) | |
| download | llvm-d7283d9c54dbc45d47ee0fbed0fbdcbf0ae74f23.tar.gz llvm-d7283d9c54dbc45d47ee0fbed0fbdcbf0ae74f23.tar.bz2 llvm-d7283d9c54dbc45d47ee0fbed0fbdcbf0ae74f23.tar.xz | |
Added for disassembly VLD1 (multiple single elements) which loads memory into
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.
A8.6.307 & A8.6.310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96980 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index ef81d65c86..d2c26e5c7b 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -191,6 +191,29 @@ def VLD1q32 : VLD1Q<0b1000, "vld1", "32", v4i32, int_arm_neon_vld1>; def VLD1qf : VLD1Q<0b1000, "vld1", "32", v4f32, int_arm_neon_vld1>; def VLD1q64 : VLD1Q<0b1100, "vld1", "64", v2i64, int_arm_neon_vld1>; +// These (dreg triple/quadruple) are for disassembly only. +class VLD1D3<bits<4> op7_4, string OpcodeStr, string Dt> + : NLdSt<0, 0b10, 0b0110, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), + (ins addrmode6:$addr), IIC_VLD1, OpcodeStr, Dt, + "\\{$dst1, $dst2, $dst3\\}, $addr", "", + [/* For disassembly only; pattern left blank */]>; +class VLD1D4<bits<4> op7_4, string OpcodeStr, string Dt> + : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), + (ins addrmode6:$addr), IIC_VLD1, OpcodeStr, Dt, + "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", + [/* For disassembly only; pattern left blank */]>; + +def VLD1d8T : VLD1D3<0b0000, "vld1", "8">; +def VLD1d16T : VLD1D3<0b0100, "vld1", "16">; +def VLD1d32T : VLD1D3<0b1000, "vld1", "32">; +//def VLD1d64T : VLD1D3<0b1100, "vld1", "64">; + +def VLD1d8Q : VLD1D4<0b0000, "vld1", "8">; +def VLD1d16Q : VLD1D4<0b0100, "vld1", "16">; +def VLD1d32Q : VLD1D4<0b1000, "vld1", "32">; +//def VLD1d64Q : VLD1D4<0b1100, "vld1", "64">; + + let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { // VLD2 : Vector Load (multiple 2-element structures) @@ -216,6 +239,16 @@ def VLD2q8 : VLD2Q<0b0000, "vld2", "8">; def VLD2q16 : VLD2Q<0b0100, "vld2", "16">; def VLD2q32 : VLD2Q<0b1000, "vld2", "32">; +// These (double-spaced dreg pair) are for disassembly only. +class VLD2Ddbl<bits<4> op7_4, string OpcodeStr, string Dt> + : NLdSt<0,0b10,0b1001,op7_4, (outs DPR:$dst1, DPR:$dst2), + (ins addrmode6:$addr), IIC_VLD2, + OpcodeStr, Dt, "\\{$dst1, $dst2\\}, $addr", "", []>; + +def VLD2d8D : VLD2Ddbl<0b0000, "vld2", "8">; +def VLD2d16D : VLD2Ddbl<0b0100, "vld2", "16">; +def VLD2d32D : VLD2Ddbl<0b1000, "vld2", "32">; + // VLD3 : Vector Load (multiple 3-element structures) class VLD3D<bits<4> op7_4, string OpcodeStr, string Dt> : NLdSt<0,0b10,0b0100,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), |